part5.tan.summary

来自「基于FPGA的CPU设计 VHDL 编写」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.324 ns
From           : SW[17]
To             : ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg7
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.172 ns
From           : ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~portb_address_reg4
To             : HEX1[1]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.087 ns
From           : SW[17]
To             : LEDG[0]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.359 ns
From           : SW[4]
To             : ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated|ram_block1a0~porta_datain_reg4
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : N/A
Required Time  : None
Actual Time    : 216.59 MHz ( period = 4.617 ns )
From           : count[14]
To             : read_addr[0]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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