part5.map.rpt

基于FPGA的CPU设计 VHDL 编写

; WIDTH_A                            ; 8               ; Integer                              ;
; WIDTHAD_A                          ; 5               ; Integer                              ;
; NUMWORDS_A                         ; 32              ; Integer                              ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                              ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                              ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                              ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                              ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                              ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                              ;
; WIDTH_B                            ; 8               ; Integer                              ;
; WIDTHAD_B                          ; 5               ; Integer                              ;
; NUMWORDS_B                         ; 32              ; Integer                              ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                              ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                              ;
; ADDRESS_REG_B                      ; CLOCK0          ; Untyped                              ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                              ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                              ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                              ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                              ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                              ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                              ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                              ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                              ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                              ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                              ;
; RAM_BLOCK_TYPE                     ; M4K             ; Untyped                              ;
; BYTE_SIZE                          ; 8               ; Untyped                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                              ;
; INIT_FILE                          ; ramlpm.mif      ; Untyped                              ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                              ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                              ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                              ;
; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                              ;
; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                              ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                              ;
; CBXI_PARAMETER                     ; altsyncram_1qi1 ; Untyped                              ;
+------------------------------------+-----------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/quartus51/exercise/lab8/part5/part5.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Apr 19 14:23:15 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part5 -c part5
Info: Found 1 design units, including 1 entities, in source file part5.v
    Info: Found entity 1: part5
Info: Elaborating entity "part5" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at part5.v(28): truncated value with size 32 to match size of target (26)
Warning (10230): Verilog HDL assignment warning at part5.v(33): truncated value with size 32 to match size of target (5)
Warning (10034): Output port "LEDG[7]" at part5.v(7) has no driver
Warning (10034): Output port "LEDG[6]" at part5.v(7) has no driver
Warning (10034): Output port "LEDG[5]" at part5.v(7) has no driver
Warning (10034): Output port "LEDG[4]" at part5.v(7) has no driver
Warning (10034): Output port "LEDG[3]" at part5.v(7) has no driver
Warning (10034): Output port "LEDG[2]" at part5.v(7) has no driver
Warning (10034): Output port "LEDG[1]" at part5.v(7) has no driver
Warning: Using design file ramlpm.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ramlpm
Info: Elaborating entity "ramlpm" for hierarchy "ramlpm:comb_42"
Info: Found 1 design units, including 1 entities, in source file ../../../libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "ramlpm:comb_42|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_1qi1.tdf
    Info: Found entity 1: altsyncram_1qi1
Info: Elaborating entity "altsyncram_1qi1" for hierarchy "ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_1qi1:auto_generated"
Warning: Using design file SEG7_LUT.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SEG7_LUT
Info: Elaborating entity "SEG7_LUT" for hierarchy "SEG7_LUT:u1"
Warning: Port "iDIG" on the entity instantiation of "u7" is connected to a signal of width 1. The formal width of the signal in the module is 4.  Extra bits will be driven by GND.
Warning: Port "iDIG" on the entity instantiation of "u3" is connected to a signal of width 1. The formal width of the signal in the module is 4.  Extra bits will be driven by GND.
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "LEDG[1]" stuck at GND
    Warning: Pin "LEDG[2]" stuck at GND
    Warning: Pin "LEDG[3]" stuck at GND
    Warning: Pin "LEDG[4]" stuck at GND
    Warning: Pin "LEDG[5]" stuck at GND
    Warning: Pin "LEDG[6]" stuck at GND
    Warning: Pin "LEDG[7]" stuck at GND
    Warning: Pin "HEX3[1]" stuck at GND
    Warning: Pin "HEX3[2]" stuck at GND
    Warning: Pin "HEX3[6]" stuck at VCC
    Warning: Pin "HEX7[1]" stuck at GND
    Warning: Pin "HEX7[2]" stuck at GND
    Warning: Pin "HEX7[6]" stuck at VCC
Warning: Design contains 7 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "SW[8]"
    Warning: No output dependent on input pin "SW[9]"
    Warning: No output dependent on input pin "SW[10]"
    Warning: No output dependent on input pin "SW[16]"
    Warning: No output dependent on input pin "KEY[1]"
    Warning: No output dependent on input pin "KEY[2]"
    Warning: No output dependent on input pin "KEY[3]"
Info: Implemented 175 device resources after synthesis - the final resource count might be different
    Info: Implemented 23 input pins
    Info: Implemented 64 output pins
    Info: Implemented 80 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 35 warnings
    Info: Processing ended: Thu Apr 19 14:23:18 2007
    Info: Elapsed time: 00:00:03