part7.tan.summary

来自「基于FPGA的CPU设计 VHDL 编写」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.774 ns
From           : SW[15]
To             : ADDR[4]
From Clock     : --
To Clock       : KEY[0]
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.845 ns
From           : OE_N
To             : SRAM_DQ[10]
From Clock     : KEY[0]
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 11.042 ns
From           : SRAM_DQ[5]
To             : HEX1[2]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.557 ns
From           : SW[11]
To             : ADDR[0]
From Clock     : --
To Clock       : KEY[0]
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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