part7.map.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 19 16:16:02 2007 " "Info: Processing started: Thu Apr 19 16:16:02 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part7 -c part7 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part7 -c part7" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part7.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file part7.v" { { "Info" "ISGN_ENTITY_NAME" "1 part7 " "Info: Found entity 1: part7" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part7 " "Info: Elaborating entity \"part7\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "LEDG part7.v(18) " "Info (10035): Verilog HDL or VHDL information at part7.v(18): object \"LEDG\" declared but not used" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 18 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "HEX2 part7.v(19) " "Info (10035): Verilog HDL or VHDL information at part7.v(19): object \"HEX2\" declared but not used" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 19 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "HEX3 part7.v(19) " "Info (10035): Verilog HDL or VHDL information at part7.v(19): object \"HEX3\" declared but not used" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 19 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "iOE_N part7.v(24) " "Info (10035): Verilog HDL or VHDL information at part7.v(24): object \"iOE_N\" declared but not used" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 24 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "18 5 part7.v(66) " "Warning (10230): Verilog HDL assignment warning at part7.v(66): truncated value with size 18 to match size of target (5)" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 8 part7.v(67) " "Warning (10230): Verilog HDL assignment warning at part7.v(67): truncated value with size 16 to match size of target (8)" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 67 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[7\] part7.v(18) " "Warning (10034): Output port \"LEDG\[7\]\" at part7.v(18) has no driver" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 18 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[6\] part7.v(18) " "Warning (10034): Output port \"LEDG\[6\]\" at part7.v(18) has no driver" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 18 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[5\] part7.v(18) " "Warning (10034): Output port \"LEDG\[5\]\" at part7.v(18) has no driver" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 18 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[4\] part7.v(18) " "Warning (10034): Output port \"LEDG\[4\]\" at part7.v(18) has no driver" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 18 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[3\] part7.v(18) " "Warning (10034): Output port \"LEDG\[3\]\" at part7.v(18) has no driver" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 18 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[2\] part7.v(18) " "Warning (10034): Output port \"LEDG\[2\]\" at part7.v(18) has no driver" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 18 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[1\] part7.v(18) " "Warning (10034): Output port \"LEDG\[1\]\" at part7.v(18) has no driver" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 18 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[0\] part7.v(18) " "Warning (10034): Output port \"LEDG\[0\]\" at part7.v(18) has no driver" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 18 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "HEX2\[6\] part7.v(19) " "Warning (10034): Output port \"HEX2\[6\]\" at part7.v(19) has no driver" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "HEX2\[5\] part7.v(19) " "Warning (10034): Output port \"HEX2\[5\]\" at part7.v(19) has no driver" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}