part7.hier_info

基于FPGA的CPU设计 VHDL 编写

|part7
SW[0] => SW[0]~7.IN1
SW[1] => SW[1]~6.IN1
SW[2] => SW[2]~5.IN1
SW[3] => SW[3]~4.IN1
SW[4] => SW[4]~3.IN1
SW[5] => SW[5]~2.IN1
SW[6] => SW[6]~1.IN1
SW[7] => SW[7]~0.IN1
SW[8] => ~NO_FANOUT~
SW[9] => ~NO_FANOUT~
SW[10] => ~NO_FANOUT~
SW[11] => SW[11]~12.IN1
SW[12] => SW[12]~11.IN1
SW[13] => SW[13]~10.IN1
SW[14] => SW[14]~9.IN1
SW[15] => SW[15]~8.IN1
SW[16] => ~NO_FANOUT~
SW[17] => OE_N.DATAIN
SW[17] => WE_N.DATAIN
KEY[0] => OE_N.CLK
KEY[0] => ADDR[4].CLK
KEY[0] => ADDR[3].CLK
KEY[0] => ADDR[2].CLK
KEY[0] => ADDR[1].CLK
KEY[0] => ADDR[0].CLK
KEY[0] => DATA[7].CLK
KEY[0] => DATA[6].CLK
KEY[0] => DATA[5].CLK
KEY[0] => DATA[4].CLK
KEY[0] => DATA[3].CLK
KEY[0] => DATA[2].CLK
KEY[0] => DATA[1].CLK
KEY[0] => DATA[0].CLK
KEY[0] => WE_N.CLK
KEY[1] => ~NO_FANOUT~
KEY[2] => ~NO_FANOUT~
KEY[3] => ~NO_FANOUT~
LEDG[0] <= <GND>
LEDG[1] <= <GND>
LEDG[2] <= <GND>
LEDG[3] <= <GND>
LEDG[4] <= <GND>
LEDG[5] <= <GND>
LEDG[6] <= <GND>
LEDG[7] <= <GND>
HEX0[0] <= SEG7_LUT:u6.oSEG
HEX0[1] <= SEG7_LUT:u6.oSEG
HEX0[2] <= SEG7_LUT:u6.oSEG
HEX0[3] <= SEG7_LUT:u6.oSEG
HEX0[4] <= SEG7_LUT:u6.oSEG
HEX0[5] <= SEG7_LUT:u6.oSEG
HEX0[6] <= SEG7_LUT:u6.oSEG
HEX1[0] <= SEG7_LUT:u5.oSEG
HEX1[1] <= SEG7_LUT:u5.oSEG
HEX1[2] <= SEG7_LUT:u5.oSEG
HEX1[3] <= SEG7_LUT:u5.oSEG
HEX1[4] <= SEG7_LUT:u5.oSEG
HEX1[5] <= SEG7_LUT:u5.oSEG
HEX1[6] <= SEG7_LUT:u5.oSEG
HEX2[0] <= <GND>
HEX2[1] <= <GND>
HEX2[2] <= <GND>
HEX2[3] <= <GND>
HEX2[4] <= <GND>
HEX2[5] <= <GND>
HEX2[6] <= <GND>
HEX3[0] <= <GND>
HEX3[1] <= <GND>
HEX3[2] <= <GND>
HEX3[3] <= <GND>
HEX3[4] <= <GND>
HEX3[5] <= <GND>
HEX3[6] <= <GND>
HEX4[0] <= SEG7_LUT:u4.oSEG
HEX4[1] <= SEG7_LUT:u4.oSEG
HEX4[2] <= SEG7_LUT:u4.oSEG
HEX4[3] <= SEG7_LUT:u4.oSEG
HEX4[4] <= SEG7_LUT:u4.oSEG
HEX4[5] <= SEG7_LUT:u4.oSEG
HEX4[6] <= SEG7_LUT:u4.oSEG
HEX5[0] <= SEG7_LUT:u3.oSEG
HEX5[1] <= SEG7_LUT:u3.oSEG
HEX5[2] <= SEG7_LUT:u3.oSEG
HEX5[3] <= SEG7_LUT:u3.oSEG
HEX5[4] <= SEG7_LUT:u3.oSEG
HEX5[5] <= SEG7_LUT:u3.oSEG
HEX5[6] <= SEG7_LUT:u3.oSEG
HEX6[0] <= SEG7_LUT:u1.oSEG
HEX6[1] <= SEG7_LUT:u1.oSEG
HEX6[2] <= SEG7_LUT:u1.oSEG
HEX6[3] <= SEG7_LUT:u1.oSEG
HEX6[4] <= SEG7_LUT:u1.oSEG
HEX6[5] <= SEG7_LUT:u1.oSEG
HEX6[6] <= SEG7_LUT:u1.oSEG
HEX7[0] <= SEG7_LUT:u2.oSEG
HEX7[1] <= SEG7_LUT:u2.oSEG
HEX7[2] <= SEG7_LUT:u2.oSEG
HEX7[3] <= SEG7_LUT:u2.oSEG
HEX7[4] <= SEG7_LUT:u2.oSEG
HEX7[5] <= SEG7_LUT:u2.oSEG
HEX7[6] <= SEG7_LUT:u2.oSEG
SRAM_DQ[0] <= SRAM_DQ~23
SRAM_DQ[0] <= SEG7_LUT:u6.iDIG
SRAM_DQ[1] <= SRAM_DQ~22
SRAM_DQ[1] <= SEG7_LUT:u6.iDIG
SRAM_DQ[2] <= SRAM_DQ~21
SRAM_DQ[2] <= SEG7_LUT:u6.iDIG
SRAM_DQ[3] <= SRAM_DQ~20
SRAM_DQ[3] <= SEG7_LUT:u6.iDIG
SRAM_DQ[4] <= SRAM_DQ~19
SRAM_DQ[4] <= SEG7_LUT:u5.iDIG
SRAM_DQ[5] <= SRAM_DQ~18
SRAM_DQ[5] <= SEG7_LUT:u5.iDIG
SRAM_DQ[6] <= SRAM_DQ~17
SRAM_DQ[6] <= SEG7_LUT:u5.iDIG
SRAM_DQ[7] <= SRAM_DQ~16
SRAM_DQ[7] <= SEG7_LUT:u5.iDIG
SRAM_DQ[8] <= SRAM_DQ~15
SRAM_DQ[9] <= SRAM_DQ~14
SRAM_DQ[10] <= SRAM_DQ~13
SRAM_DQ[11] <= SRAM_DQ~12
SRAM_DQ[12] <= SRAM_DQ~11
SRAM_DQ[13] <= SRAM_DQ~10
SRAM_DQ[14] <= SRAM_DQ~9
SRAM_DQ[15] <= SRAM_DQ~8
SRAM_ADDR[0] <= ADDR[0].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[1] <= ADDR[1].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[2] <= ADDR[2].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[3] <= ADDR[3].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[4] <= ADDR[4].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[5] <= <GND>
SRAM_ADDR[6] <= <GND>
SRAM_ADDR[7] <= <GND>
SRAM_ADDR[8] <= <GND>
SRAM_ADDR[9] <= <GND>
SRAM_ADDR[10] <= <GND>
SRAM_ADDR[11] <= <GND>
SRAM_ADDR[12] <= <GND>
SRAM_ADDR[13] <= <GND>
SRAM_ADDR[14] <= <GND>
SRAM_ADDR[15] <= <GND>
SRAM_ADDR[16] <= <GND>
SRAM_ADDR[17] <= <GND>
SRAM_UB_N <= <GND>
SRAM_LB_N <= <GND>
SRAM_WE_N <= WE_N.DB_MAX_OUTPUT_PORT_TYPE
SRAM_CE_N <= <GND>
SRAM_OE_N <= OE_N.DB_MAX_OUTPUT_PORT_TYPE


|part7|SEG7_LUT:u1
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|part7|SEG7_LUT:u2
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|part7|SEG7_LUT:u3
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|part7|SEG7_LUT:u4
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|part7|SEG7_LUT:u5
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|part7|SEG7_LUT:u6
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0