part7.hif

基于FPGA的CPU设计 VHDL 编写

Version 5.1 Build 176 10/26/2005 SJ Full Version
10
763
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
part7
# storage
db|part7.(0).cnf
db|part7.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
part7.v
90f532e89969994d86fee82589ea2
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
SEG7_LUT
# storage
db|part7.(1).cnf
db|part7.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SEG7_LUT.v
2d28569a9628f555c8ab6189be7f6e
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SEG7_LUT:u1
SEG7_LUT:u2
SEG7_LUT:u3
SEG7_LUT:u4
SEG7_LUT:u5
SEG7_LUT:u6
}
# end
# complete