part7.tan.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "ITDB_FULL_TCO_RESULT" "KEY\[0\] SRAM_DQ\[11\] OE_N 9.845 ns register " "Info: tco from clock \"KEY\[0\]\" to destination pin \"SRAM_DQ\[11\]\" through register \"OE_N\" is 9.845 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY\[0\] source 4.165 ns + Longest register " "Info: + Longest clock path from clock \"KEY\[0\]\" to source register is 4.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns KEY\[0\] 1 CLK PIN_G26 14 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_G26; Fanout = 14; CLK Node = 'KEY\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "" { KEY[0] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.776 ns) + CELL(0.537 ns) 4.165 ns OE_N 2 REG LCFF_X1_Y14_N1 18 " "Info: 2: + IC(2.776 ns) + CELL(0.537 ns) = 4.165 ns; Loc. = LCFF_X1_Y14_N1; Fanout = 18; REG Node = 'OE_N'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "3.313 ns" { KEY[0] OE_N } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.389 ns ( 33.35 % ) " "Info: Total cell delay = 1.389 ns ( 33.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.776 ns ( 66.65 % ) " "Info: Total interconnect delay = 2.776 ns ( 66.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "4.165 ns" { KEY[0] OE_N } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.165 ns" { KEY[0] KEY[0]~combout OE_N } { 0.000ns 0.000ns 2.776ns } { 0.000ns 0.852ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.430 ns + Longest register pin " "Info: + Longest register to pin delay is 5.430 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns OE_N 1 REG LCFF_X1_Y14_N1 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y14_N1; Fanout = 18; REG Node = 'OE_N'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "" { OE_N } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.632 ns) + CELL(2.798 ns) 5.430 ns SRAM_DQ\[11\] 2 PIN PIN_AF8 0 " "Info: 2: + IC(2.632 ns) + CELL(2.798 ns) = 5.430 ns; Loc. = PIN_AF8; Fanout = 0; PIN Node = 'SRAM_DQ\[11\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "5.430 ns" { OE_N SRAM_DQ[11] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 51.53 % ) " "Info: Total cell delay = 2.798 ns ( 51.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.632 ns ( 48.47 % ) " "Info: Total interconnect delay = 2.632 ns ( 48.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "5.430 ns" { OE_N SRAM_DQ[11] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.430 ns" { OE_N SRAM_DQ[11] } { 0.000ns 2.632ns } { 0.000ns 2.798ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "4.165 ns" { KEY[0] OE_N } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.165 ns" { KEY[0] KEY[0]~combout OE_N } { 0.000ns 0.000ns 2.776ns } { 0.000ns 0.852ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "5.430 ns" { OE_N SRAM_DQ[11] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.430 ns" { OE_N SRAM_DQ[11] } { 0.000ns 2.632ns } { 0.000ns 2.798ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SRAM_DQ\[5\] HEX1\[2\] 11.042 ns Longest " "Info: Longest tpd from source pin \"SRAM_DQ\[5\]\" to destination pin \"HEX1\[2\]\" is 11.042 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SRAM_DQ\[5\] 1 PIN PIN_AB10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB10; Fanout = 1; PIN Node = 'SRAM_DQ\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "" { SRAM_DQ[5] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.820 ns) 0.820 ns oDATA\[5\] 2 COMB IOC_X14_Y0_N1 7 " "Info: 2: + IC(0.000 ns) + CELL(0.820 ns) = 0.820 ns; Loc. = IOC_X14_Y0_N1; Fanout = 7; COMB Node = 'oDATA\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "0.820 ns" { SRAM_DQ[5] oDATA[5] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.434 ns) + CELL(0.438 ns) 7.692 ns SEG7_LUT:u5\|oSEG\[2\]~72 3 COMB LCCOMB_X64_Y3_N20 1 " "Info: 3: + IC(6.434 ns) + CELL(0.438 ns) = 7.692 ns; Loc. = LCCOMB_X64_Y3_N20; Fanout = 1; COMB Node = 'SEG7_LUT:u5\|oSEG\[2\]~72'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "6.872 ns" { oDATA[5] SEG7_LUT:u5|oSEG[2]~72 } "NODE_NAME" } "" } } { "SEG7_LUT.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/SEG7_LUT.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.738 ns) + CELL(2.612 ns) 11.042 ns HEX1\[2\] 4 PIN PIN_W21 0 " "Info: 4: + IC(0.738 ns) + CELL(2.612 ns) = 11.042 ns; Loc. = PIN_W21; Fanout = 0; PIN Node = 'HEX1\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "3.350 ns" { SEG7_LUT:u5|oSEG[2]~72 HEX1[2] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.870 ns ( 35.05 % ) " "Info: Total cell delay = 3.870 ns ( 35.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.172 ns ( 64.95 % ) " "Info: Total interconnect delay = 7.172 ns ( 64.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "11.042 ns" { SRAM_DQ[5] oDATA[5] SEG7_LUT:u5|oSEG[2]~72 HEX1[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.042 ns" { SRAM_DQ[5] oDATA[5] SEG7_LUT:u5|oSEG[2]~72 HEX1[2] } { 0.000ns 0.000ns 6.434ns 0.738ns } { 0.000ns 0.820ns 0.438ns 2.612ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "ADDR\[0\] SW\[11\] KEY\[0\] 2.557 ns register " "Info: th for register \"ADDR\[0\]\" (data pin = \"SW\[11\]\", clock pin = \"KEY\[0\]\") is 2.557 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY\[0\] destination 4.165 ns + Longest register " "Info: + Longest clock path from clock \"KEY\[0\]\" to destination register is 4.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns KEY\[0\] 1 CLK PIN_G26 14 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_G26; Fanout = 14; CLK Node = 'KEY\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "" { KEY[0] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.776 ns) + CELL(0.537 ns) 4.165 ns ADDR\[0\] 2 REG LCFF_X1_Y14_N21 1 " "Info: 2: + IC(2.776 ns) + CELL(0.537 ns) = 4.165 ns; Loc. = LCFF_X1_Y14_N21; Fanout = 1; REG Node = 'ADDR\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "3.313 ns" { KEY[0] ADDR[0] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.389 ns ( 33.35 % ) " "Info: Total cell delay = 1.389 ns ( 33.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.776 ns ( 66.65 % ) " "Info: Total interconnect delay = 2.776 ns ( 66.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "4.165 ns" { KEY[0] ADDR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.165 ns" { KEY[0] KEY[0]~combout ADDR[0] } { 0.000ns 0.000ns 2.776ns } { 0.000ns 0.852ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 68 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.874 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns SW\[11\] 1 PIN PIN_P1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_P1; Fanout = 8; PIN Node = 'SW\[11\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "" { SW[11] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.652 ns) + CELL(0.149 ns) 1.790 ns ADDR\[0\]~feeder 2 COMB LCCOMB_X1_Y14_N20 1 " "Info: 2: + IC(0.652 ns) + CELL(0.149 ns) = 1.790 ns; Loc. = LCCOMB_X1_Y14_N20; Fanout = 1; COMB Node = 'ADDR\[0\]~feeder'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "0.801 ns" { SW[11] ADDR[0]~feeder } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.874 ns ADDR\[0\] 3 REG LCFF_X1_Y14_N21 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.874 ns; Loc. = LCFF_X1_Y14_N21; Fanout = 1; REG Node = 'ADDR\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "0.084 ns" { ADDR[0]~feeder ADDR[0] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns ( 65.21 % ) " "Info: Total cell delay = 1.222 ns ( 65.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.652 ns ( 34.79 % ) " "Info: Total interconnect delay = 0.652 ns ( 34.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "1.874 ns" { SW[11] ADDR[0]~feeder ADDR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.874 ns" { SW[11] SW[11]~combout ADDR[0]~feeder ADDR[0] } { 0.000ns 0.000ns 0.652ns 0.000ns } { 0.000ns 0.989ns 0.149ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "4.165 ns" { KEY[0] ADDR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.165 ns" { KEY[0] KEY[0]~combout ADDR[0] } { 0.000ns 0.000ns 2.776ns } { 0.000ns 0.852ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "1.874 ns" { SW[11] ADDR[0]~feeder ADDR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.874 ns" { SW[11] SW[11]~combout ADDR[0]~feeder ADDR[0] } { 0.000ns 0.000ns 0.652ns 0.000ns } { 0.000ns 0.989ns 0.149ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 19 16:16:32 2007 " "Info: Processing ended: Thu Apr 19 16:16:32 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}