part7.tan.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 19 16:16:31 2007 " "Info: Processing started: Thu Apr 19 16:16:31 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off part7 -c part7 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part7 -c part7 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "KEY\[0\] " "Info: Assuming node \"KEY\[0\]\" is an undefined clock" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 17 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "KEY\[0\] " "Info: No valid register-to-register data paths exist for clock \"KEY\[0\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ADDR\[4\] SW\[15\] KEY\[0\] 1.774 ns register " "Info: tsu for register \"ADDR\[4\]\" (data pin = \"SW\[15\]\", clock pin = \"KEY\[0\]\") is 1.774 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.975 ns + Longest pin register " "Info: + Longest pin to register delay is 5.975 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns SW\[15\] 1 PIN PIN_U4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_U4; Fanout = 5; PIN Node = 'SW\[15\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "" { SW[15] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.777 ns) + CELL(0.366 ns) 5.975 ns ADDR\[4\] 2 REG LCFF_X1_Y14_N5 1 " "Info: 2: + IC(4.777 ns) + CELL(0.366 ns) = 5.975 ns; Loc. = LCFF_X1_Y14_N5; Fanout = 1; REG Node = 'ADDR\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "5.143 ns" { SW[15] ADDR[4] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.198 ns ( 20.05 % ) " "Info: Total cell delay = 1.198 ns ( 20.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.777 ns ( 79.95 % ) " "Info: Total interconnect delay = 4.777 ns ( 79.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "5.975 ns" { SW[15] ADDR[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.975 ns" { SW[15] SW[15]~combout ADDR[4] } { 0.000ns 0.000ns 4.777ns } { 0.000ns 0.832ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 68 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY\[0\] destination 4.165 ns - Shortest register " "Info: - Shortest clock path from clock \"KEY\[0\]\" to destination register is 4.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns KEY\[0\] 1 CLK PIN_G26 14 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_G26; Fanout = 14; CLK Node = 'KEY\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "" { KEY[0] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.776 ns) + CELL(0.537 ns) 4.165 ns ADDR\[4\] 2 REG LCFF_X1_Y14_N5 1 " "Info: 2: + IC(2.776 ns) + CELL(0.537 ns) = 4.165 ns; Loc. = LCFF_X1_Y14_N5; Fanout = 1; REG Node = 'ADDR\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "3.313 ns" { KEY[0] ADDR[4] } "NODE_NAME" } "" } } { "part7.v" "" { Text "C:/altera/quartus51/exercise/lab8/part7/part7.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.389 ns ( 33.35 % ) " "Info: Total cell delay = 1.389 ns ( 33.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.776 ns ( 66.65 % ) " "Info: Total interconnect delay = 2.776 ns ( 66.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "4.165 ns" { KEY[0] ADDR[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.165 ns" { KEY[0] KEY[0]~combout ADDR[4] } { 0.000ns 0.000ns 2.776ns } { 0.000ns 0.852ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "5.975 ns" { SW[15] ADDR[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.975 ns" { SW[15] SW[15]~combout ADDR[4] } { 0.000ns 0.000ns 4.777ns } { 0.000ns 0.832ns 0.366ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part7" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part7/db/part7.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part7/" "" "4.165 ns" { KEY[0] ADDR[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.165 ns" { KEY[0] KEY[0]~combout ADDR[4] } { 0.000ns 0.000ns 2.776ns } { 0.000ns 0.852ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}