part7.fit.summary

基于FPGA的CPU设计 VHDL 编写

Fitter Status : Successful - Thu Apr 19 16:16:18 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : part7
Top-level Entity Name : part7
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Preliminary
Total logic elements : 49 / 33,216 ( < 1 % )
Total registers : 14
Total pins : 125 / 475 ( 26 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )