part7.map.rpt

基于FPGA的CPU设计 VHDL 编写

; Average fan-out                             ; 1.37  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |part7                     ; 35 (0)            ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 125  ; 0            ; |part7              ;
;    |SEG7_LUT:u1|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part7|SEG7_LUT:u1  ;
;    |SEG7_LUT:u3|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part7|SEG7_LUT:u3  ;
;    |SEG7_LUT:u4|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part7|SEG7_LUT:u4  ;
;    |SEG7_LUT:u5|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part7|SEG7_LUT:u5  ;
;    |SEG7_LUT:u6|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part7|SEG7_LUT:u6  ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 14    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/quartus51/exercise/lab8/part7/part7.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Apr 19 16:16:02 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part7 -c part7
Info: Found 1 design units, including 1 entities, in source file part7.v
    Info: Found entity 1: part7
Info: Elaborating entity "part7" for the top level hierarchy
Info (10035): Verilog HDL or VHDL information at part7.v(18): object "LEDG" declared but not used
Info (10035): Verilog HDL or VHDL information at part7.v(19): object "HEX2" declared but not used
Info (10035): Verilog HDL or VHDL information at part7.v(19): object "HEX3" declared but not used
Info (10035): Verilog HDL or VHDL information at part7.v(24): object "iOE_N" declared but not used
Warning (10230): Verilog HDL assignment warning at part7.v(66): truncated value with size 18 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at part7.v(67): truncated value with size 16 to match size of target (8)
Warning (10034): Output port "LEDG[7]" at part7.v(18) has no driver
Warning (10034): Output port "LEDG[6]" at part7.v(18) has no driver
Warning (10034): Output port "LEDG[5]" at part7.v(18) has no driver
Warning (10034): Output port "LEDG[4]" at part7.v(18) has no driver
Warning (10034): Output port "LEDG[3]" at part7.v(18) has no driver
Warning (10034): Output port "LEDG[2]" at part7.v(18) has no driver
Warning (10034): Output port "LEDG[1]" at part7.v(18) has no driver
Warning (10034): Output port "LEDG[0]" at part7.v(18) has no driver
Warning (10034): Output port "HEX2[6]" at part7.v(19) has no driver
Warning (10034): Output port "HEX2[5]" at part7.v(19) has no driver
Warning (10034): Output port "HEX2[4]" at part7.v(19) has no driver
Warning (10034): Output port "HEX2[3]" at part7.v(19) has no driver
Warning (10034): Output port "HEX2[2]" at part7.v(19) has no driver
Warning (10034): Output port "HEX2[1]" at part7.v(19) has no driver
Warning (10034): Output port "HEX2[0]" at part7.v(19) has no driver
Warning (10034): Output port "HEX3[6]" at part7.v(19) has no driver
Warning (10034): Output port "HEX3[5]" at part7.v(19) has no driver
Warning (10034): Output port "HEX3[4]" at part7.v(19) has no driver
Warning (10034): Output port "HEX3[3]" at part7.v(19) has no driver
Warning (10034): Output port "HEX3[2]" at part7.v(19) has no driver
Warning (10034): Output port "HEX3[1]" at part7.v(19) has no driver
Warning (10034): Output port "HEX3[0]" at part7.v(19) has no driver
Warning: Using design file SEG7_LUT.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SEG7_LUT
Info: Elaborating entity "SEG7_LUT" for hierarchy "SEG7_LUT:u1"
Warning: Port "iDIG" on the entity instantiation of "u2" is connected to a signal of width 1. The formal width of the signal in the module is 4.  Extra bits will be driven by GND.
Info: Duplicate registers merged to single register
    Info: Duplicate register "WE_N" merged to single register "OE_N", power-up level changed
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "LEDG[0]" stuck at GND
    Warning: Pin "LEDG[1]" stuck at GND
    Warning: Pin "LEDG[2]" stuck at GND
    Warning: Pin "LEDG[3]" stuck at GND
    Warning: Pin "LEDG[4]" stuck at GND
    Warning: Pin "LEDG[5]" stuck at GND
    Warning: Pin "LEDG[6]" stuck at GND
    Warning: Pin "LEDG[7]" stuck at GND
    Warning: Pin "HEX2[0]" stuck at GND
    Warning: Pin "HEX2[1]" stuck at GND
    Warning: Pin "HEX2[2]" stuck at GND
    Warning: Pin "HEX2[3]" stuck at GND
    Warning: Pin "HEX2[4]" stuck at GND
    Warning: Pin "HEX2[5]" stuck at GND
    Warning: Pin "HEX2[6]" stuck at GND
    Warning: Pin "HEX3[0]" stuck at GND
    Warning: Pin "HEX3[1]" stuck at GND
    Warning: Pin "HEX3[2]" stuck at GND
    Warning: Pin "HEX3[3]" stuck at GND
    Warning: Pin "HEX3[4]" stuck at GND
    Warning: Pin "HEX3[5]" stuck at GND
    Warning: Pin "HEX3[6]" stuck at GND
    Warning: Pin "HEX7[1]" stuck at GND
    Warning: Pin "HEX7[2]" stuck at GND
    Warning: Pin "HEX7[6]" stuck at VCC
    Warning: Pin "SRAM_ADDR[5]" stuck at GND
    Warning: Pin "SRAM_ADDR[6]" stuck at GND
    Warning: Pin "SRAM_ADDR[7]" stuck at GND
    Warning: Pin "SRAM_ADDR[8]" stuck at GND
    Warning: Pin "SRAM_ADDR[9]" stuck at GND
    Warning: Pin "SRAM_ADDR[10]" stuck at GND
    Warning: Pin "SRAM_ADDR[11]" stuck at GND
    Warning: Pin "SRAM_ADDR[12]" stuck at GND
    Warning: Pin "SRAM_ADDR[13]" stuck at GND
    Warning: Pin "SRAM_ADDR[14]" stuck at GND
    Warning: Pin "SRAM_ADDR[15]" stuck at GND
    Warning: Pin "SRAM_ADDR[16]" stuck at GND
    Warning: Pin "SRAM_ADDR[17]" stuck at GND
    Warning: Pin "SRAM_UB_N" stuck at GND
    Warning: Pin "SRAM_LB_N" stuck at GND
    Warning: Pin "SRAM_CE_N" stuck at GND
Warning: Design contains 7 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "SW[8]"
    Warning: No output dependent on input pin "SW[9]"
    Warning: No output dependent on input pin "SW[10]"
    Warning: No output dependent on input pin "SW[16]"
    Warning: No output dependent on input pin "KEY[1]"
    Warning: No output dependent on input pin "KEY[2]"
    Warning: No output dependent on input pin "KEY[3]"
Info: Implemented 174 device resources after synthesis - the final resource count might be different
    Info: Implemented 22 input pins
    Info: Implemented 87 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 49 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 76 warnings
    Info: Processing ended: Thu Apr 19 16:16:04 2007
    Info: Elapsed time: 00:00:02