part7.fit.eqn

基于FPGA的CPU设计 VHDL 编写

--HEX3[1] is HEX3[1] at PIN_AA25
--operation mode is output

HEX3[1] = OUTPUT(GND);


--HEX3[2] is HEX3[2] at PIN_AA26
--operation mode is output

HEX3[2] = OUTPUT(GND);


--HEX3[3] is HEX3[3] at PIN_Y26
--operation mode is output

HEX3[3] = OUTPUT(GND);


--HEX3[4] is HEX3[4] at PIN_Y25
--operation mode is output

HEX3[4] = OUTPUT(GND);


--HEX3[5] is HEX3[5] at PIN_U22
--operation mode is output

HEX3[5] = OUTPUT(GND);


--HEX3[6] is HEX3[6] at PIN_W24
--operation mode is output

HEX3[6] = OUTPUT(GND);


--HEX4[0] is HEX4[0] at PIN_U9
--operation mode is output

HEX4[0] = OUTPUT(B4L1);


--HEX4[1] is HEX4[1] at PIN_U1
--operation mode is output

HEX4[1] = OUTPUT(B4L2);


--HEX4[2] is HEX4[2] at PIN_U2
--operation mode is output

HEX4[2] = OUTPUT(B4L3);


--HEX4[3] is HEX4[3] at PIN_T4
--operation mode is output

HEX4[3] = OUTPUT(B4L4);


--HEX4[4] is HEX4[4] at PIN_R7
--operation mode is output

HEX4[4] = OUTPUT(B4L5);


--HEX4[5] is HEX4[5] at PIN_R6
--operation mode is output

HEX4[5] = OUTPUT(B4L6);


--HEX4[6] is HEX4[6] at PIN_T3
--operation mode is output

HEX4[6] = OUTPUT(!B4L7);


--HEX5[0] is HEX5[0] at PIN_T2
--operation mode is output

HEX5[0] = OUTPUT(B3L1);


--HEX5[1] is HEX5[1] at PIN_P6
--operation mode is output

HEX5[1] = OUTPUT(B3L2);


--HEX5[2] is HEX5[2] at PIN_P7
--operation mode is output

HEX5[2] = OUTPUT(B3L3);


--HEX5[3] is HEX5[3] at PIN_T9
--operation mode is output

HEX5[3] = OUTPUT(B3L4);


--HEX5[4] is HEX5[4] at PIN_R5
--operation mode is output

HEX5[4] = OUTPUT(B3L5);


--HEX5[5] is HEX5[5] at PIN_R4
--operation mode is output

HEX5[5] = OUTPUT(B3L6);


--HEX5[6] is HEX5[6] at PIN_R3
--operation mode is output

HEX5[6] = OUTPUT(!B3L7);


--HEX6[0] is HEX6[0] at PIN_R2
--operation mode is output

HEX6[0] = OUTPUT(B1L1);


--HEX6[1] is HEX6[1] at PIN_P4
--operation mode is output

HEX6[1] = OUTPUT(B1L2);


--HEX6[2] is HEX6[2] at PIN_P3
--operation mode is output

HEX6[2] = OUTPUT(B1L3);


--HEX6[3] is HEX6[3] at PIN_M2
--operation mode is output

HEX6[3] = OUTPUT(B1L4);


--HEX6[4] is HEX6[4] at PIN_M3
--operation mode is output

HEX6[4] = OUTPUT(B1L5);


--HEX6[5] is HEX6[5] at PIN_M5
--operation mode is output

HEX6[5] = OUTPUT(B1L6);


--HEX6[6] is HEX6[6] at PIN_M4
--operation mode is output

HEX6[6] = OUTPUT(!B1L7);


--HEX7[0] is HEX7[0] at PIN_L3
--operation mode is output

HEX7[0] = OUTPUT(SW[15]);


--HEX7[1] is HEX7[1] at PIN_L2
--operation mode is output

HEX7[1] = OUTPUT(GND);


--HEX7[2] is HEX7[2] at PIN_L9
--operation mode is output

HEX7[2] = OUTPUT(GND);


--HEX7[3] is HEX7[3] at PIN_L6
--operation mode is output

HEX7[3] = OUTPUT(SW[15]);


--HEX7[4] is HEX7[4] at PIN_L7
--operation mode is output

HEX7[4] = OUTPUT(SW[15]);


--HEX7[5] is HEX7[5] at PIN_P9
--operation mode is output

HEX7[5] = OUTPUT(SW[15]);


--HEX7[6] is HEX7[6] at PIN_N9
--operation mode is output

HEX7[6] = OUTPUT(VCC);


--SRAM_ADDR[0] is SRAM_ADDR[0] at PIN_AE4
--operation mode is output

SRAM_ADDR[0] = OUTPUT(ADDR[0]);


--SRAM_ADDR[1] is SRAM_ADDR[1] at PIN_AF4
--operation mode is output

SRAM_ADDR[1] = OUTPUT(ADDR[1]);


--SRAM_ADDR[2] is SRAM_ADDR[2] at PIN_AC5
--operation mode is output

SRAM_ADDR[2] = OUTPUT(ADDR[2]);


--SRAM_ADDR[3] is SRAM_ADDR[3] at PIN_AC6
--operation mode is output

SRAM_ADDR[3] = OUTPUT(ADDR[3]);


--SRAM_ADDR[4] is SRAM_ADDR[4] at PIN_AD4
--operation mode is output

SRAM_ADDR[4] = OUTPUT(ADDR[4]);


--SRAM_ADDR[5] is SRAM_ADDR[5] at PIN_AD5
--operation mode is output

SRAM_ADDR[5] = OUTPUT(GND);


--SRAM_ADDR[6] is SRAM_ADDR[6] at PIN_AE5
--operation mode is output

SRAM_ADDR[6] = OUTPUT(GND);


--SRAM_ADDR[7] is SRAM_ADDR[7] at PIN_AF5
--operation mode is output

SRAM_ADDR[7] = OUTPUT(GND);


--SRAM_ADDR[8] is SRAM_ADDR[8] at PIN_AD6
--operation mode is output

SRAM_ADDR[8] = OUTPUT(GND);


--SRAM_ADDR[9] is SRAM_ADDR[9] at PIN_AD7
--operation mode is output

SRAM_ADDR[9] = OUTPUT(GND);


--SRAM_ADDR[10] is SRAM_ADDR[10] at PIN_V10
--operation mode is output

SRAM_ADDR[10] = OUTPUT(GND);


--SRAM_ADDR[11] is SRAM_ADDR[11] at PIN_V9
--operation mode is output

SRAM_ADDR[11] = OUTPUT(GND);


--SRAM_ADDR[12] is SRAM_ADDR[12] at PIN_AC7
--operation mode is output

SRAM_ADDR[12] = OUTPUT(GND);


--SRAM_ADDR[13] is SRAM_ADDR[13] at PIN_W8
--operation mode is output

SRAM_ADDR[13] = OUTPUT(GND);


--SRAM_ADDR[14] is SRAM_ADDR[14] at PIN_W10
--operation mode is output

SRAM_ADDR[14] = OUTPUT(GND);


--SRAM_ADDR[15] is SRAM_ADDR[15] at PIN_Y10
--operation mode is output

SRAM_ADDR[15] = OUTPUT(GND);


--SRAM_ADDR[16] is SRAM_ADDR[16] at PIN_AB8
--operation mode is output

SRAM_ADDR[16] = OUTPUT(GND);


--SRAM_ADDR[17] is SRAM_ADDR[17] at PIN_AC8
--operation mode is output

SRAM_ADDR[17] = OUTPUT(GND);


--SRAM_UB_N is SRAM_UB_N at PIN_AF9
--operation mode is output

SRAM_UB_N = OUTPUT(GND);


--SRAM_LB_N is SRAM_LB_N at PIN_AE9
--operation mode is output

SRAM_LB_N = OUTPUT(GND);


--SRAM_WE_N is SRAM_WE_N at PIN_AE10
--operation mode is output

SRAM_WE_N = OUTPUT(!OE_N);


--SRAM_CE_N is SRAM_CE_N at PIN_AC11
--operation mode is output

SRAM_CE_N = OUTPUT(GND);


--SRAM_OE_N is SRAM_OE_N at PIN_AD10
--operation mode is output

SRAM_OE_N = OUTPUT(OE_N);


--oDATA[0] is oDATA[0] at PIN_AD8
--operation mode is bidir

oDATA[0] = SRAM_DQ[0];

--SRAM_DQ[0] is SRAM_DQ[0] at PIN_AD8
--operation mode is bidir

SRAM_DQ[0]_tri_out = TRI(DATA[0], OE_N);
SRAM_DQ[0] = BIDIR(SRAM_DQ[0]_tri_out);


--oDATA[1] is oDATA[1] at PIN_AE6
--operation mode is bidir

oDATA[1] = SRAM_DQ[1];

--SRAM_DQ[1] is SRAM_DQ[1] at PIN_AE6
--operation mode is bidir

SRAM_DQ[1]_tri_out = TRI(DATA[1], OE_N);
SRAM_DQ[1] = BIDIR(SRAM_DQ[1]_tri_out);


--oDATA[2] is oDATA[2] at PIN_AF6
--operation mode is bidir

oDATA[2] = SRAM_DQ[2];

--SRAM_DQ[2] is SRAM_DQ[2] at PIN_AF6
--operation mode is bidir

SRAM_DQ[2]_tri_out = TRI(DATA[2], OE_N);
SRAM_DQ[2] = BIDIR(SRAM_DQ[2]_tri_out);


--oDATA[3] is oDATA[3] at PIN_AA9
--operation mode is bidir

oDATA[3] = SRAM_DQ[3];

--SRAM_DQ[3] is SRAM_DQ[3] at PIN_AA9
--operation mode is bidir

SRAM_DQ[3]_tri_out = TRI(DATA[3], OE_N);
SRAM_DQ[3] = BIDIR(SRAM_DQ[3]_tri_out);


--oDATA[4] is oDATA[4] at PIN_AA10
--operation mode is bidir

oDATA[4] = SRAM_DQ[4];

--SRAM_DQ[4] is SRAM_DQ[4] at PIN_AA10
--operation mode is bidir

SRAM_DQ[4]_tri_out = TRI(DATA[4], OE_N);
SRAM_DQ[4] = BIDIR(SRAM_DQ[4]_tri_out);


--oDATA[5] is oDATA[5] at PIN_AB10
--operation mode is bidir

oDATA[5] = SRAM_DQ[5];

--SRAM_DQ[5] is SRAM_DQ[5] at PIN_AB10
--operation mode is bidir

SRAM_DQ[5]_tri_out = TRI(DATA[5], OE_N);
SRAM_DQ[5] = BIDIR(SRAM_DQ[5]_tri_out);


--oDATA[6] is oDATA[6] at PIN_AA11
--operation mode is bidir

oDATA[6] = SRAM_DQ[6];

--SRAM_DQ[6] is SRAM_DQ[6] at PIN_AA11
--operation mode is bidir

SRAM_DQ[6]_tri_out = TRI(DATA[6], OE_N);
SRAM_DQ[6] = BIDIR(SRAM_DQ[6]_tri_out);


--oDATA[7] is oDATA[7] at PIN_Y11
--operation mode is bidir

oDATA[7] = SRAM_DQ[7];

--SRAM_DQ[7] is SRAM_DQ[7] at PIN_Y11
--operation mode is bidir

SRAM_DQ[7]_tri_out = TRI(DATA[7], OE_N);
SRAM_DQ[7] = BIDIR(SRAM_DQ[7]_tri_out);


--SRAM_DQ[8] is SRAM_DQ[8] at PIN_AE7
--operation mode is bidir

SRAM_DQ[8] = BIDIR(OPNDRN(!OE_N));


--SRAM_DQ[9] is SRAM_DQ[9] at PIN_AF7
--operation mode is bidir

SRAM_DQ[9] = BIDIR(OPNDRN(!OE_N));


--SRAM_DQ[10] is SRAM_DQ[10] at PIN_AE8
--operation mode is bidir

SRAM_DQ[10] = BIDIR(OPNDRN(!OE_N));


--SRAM_DQ[11] is SRAM_DQ[11] at PIN_AF8
--operation mode is bidir

SRAM_DQ[11] = BIDIR(OPNDRN(!OE_N));


--SRAM_DQ[12] is SRAM_DQ[12] at PIN_W11
--operation mode is bidir

SRAM_DQ[12] = BIDIR(OPNDRN(!OE_N));


--SRAM_DQ[13] is SRAM_DQ[13] at PIN_W12
--operation mode is bidir

SRAM_DQ[13] = BIDIR(OPNDRN(!OE_N));


--SRAM_DQ[14] is SRAM_DQ[14] at PIN_AC9
--operation mode is bidir

SRAM_DQ[14] = BIDIR(OPNDRN(!OE_N));


--SRAM_DQ[15] is SRAM_DQ[15] at PIN_AC10
--operation mode is bidir

SRAM_DQ[15] = BIDIR(OPNDRN(!OE_N));





--A1L15 is DATA[2]~feeder at LCCOMB_X1_Y14_N16
A1L15 = SW[2];


--A1L18 is DATA[4]~feeder at LCCOMB_X9_Y14_N8
A1L18 = SW[4];


--A1L3 is ADDR[0]~feeder at LCCOMB_X1_Y14_N20
A1L3 = SW[11];


--A1L5 is ADDR[1]~feeder at LCCOMB_X1_Y14_N18
A1L5 = SW[12];


--A1L7 is ADDR[2]~feeder at LCCOMB_X1_Y14_N14
A1L7 = SW[13];


--A1L9 is ADDR[3]~feeder at LCCOMB_X1_Y14_N26
A1L9 = SW[14];


--A1L101 is OE_N~feeder at LCCOMB_X1_Y14_N0
A1L101 = SW[17];