part7.fit.rpt

基于FPGA的CPU设计 VHDL 编写

Fitter report for part7
Thu Apr 19 16:16:19 2007
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. Bidir Pins
 11. I/O Bank Usage
 12. All Package Pins
 13. Output Pin Default Load For Reported TCO
 14. Fitter Resource Utilization by Entity
 15. Delay Chain Summary
 16. Pad To Core Delay Chain Fanout
 17. Control Signals
 18. Non-Global High Fan-Out Signals
 19. Interconnect Usage Summary
 20. LAB Logic Elements
 21. LAB-wide Signals
 22. LAB Signals Sourced
 23. LAB Signals Sourced Out
 24. LAB Distinct Inputs
 25. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Fitter Summary                                                                ;
+------------------------------------+------------------------------------------+
; Fitter Status                      ; Successful - Thu Apr 19 16:16:18 2007    ;
; Quartus II Version                 ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name                      ; part7                                    ;
; Top-level Entity Name              ; part7                                    ;
; Family                             ; Cyclone II                               ;
; Device                             ; EP2C35F672C6                             ;
; Timing Models                      ; Preliminary                              ;
; Total logic elements               ; 49 / 33,216 ( < 1 % )                    ;
; Total registers                    ; 14                                       ;
; Total pins                         ; 125 / 475 ( 26 % )                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 0 / 483,840 ( 0 % )                      ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                           ;
; Total PLLs                         ; 0 / 4 ( 0 % )                            ;
+------------------------------------+------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                        ;
+------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                               ; Setting                        ; Default Value                  ;
+------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                               ; EP2C35F672C6                   ;                                ;
; SignalProbe signals routed during normal compilation ; Off                            ; Off                            ;