part1.tan.rpt

基于FPGA的CPU设计 VHDL 编写

; N/A           ; None        ; -2.858 ns ; ADDR[3]   ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg3 ; CLOCK    ;
; N/A           ; None        ; -2.861 ns ; ADDR[2]   ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg2 ; CLOCK    ;
; N/A           ; None        ; -3.116 ns ; DATAIN[3] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg3  ; CLOCK    ;
; N/A           ; None        ; -3.140 ns ; ADDR[1]   ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg1 ; CLOCK    ;
; N/A           ; None        ; -3.166 ns ; ADDR[4]   ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4 ; CLOCK    ;
; N/A           ; None        ; -3.177 ns ; DATAIN[6] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg6  ; CLOCK    ;
; N/A           ; None        ; -3.313 ns ; DATAIN[5] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg5  ; CLOCK    ;
; N/A           ; None        ; -3.317 ns ; DATAIN[4] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg4  ; CLOCK    ;
; N/A           ; None        ; -3.321 ns ; DATAIN[1] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg1  ; CLOCK    ;
; N/A           ; None        ; -3.342 ns ; DATAIN[7] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg7  ; CLOCK    ;
; N/A           ; None        ; -3.591 ns ; DATAIN[2] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg2  ; CLOCK    ;
; N/A           ; None        ; -3.733 ns ; ADDR[0]   ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0 ; CLOCK    ;
+---------------+-------------+-----------+-----------+----------------------------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Jul 31 16:52:54 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part1 -c part1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLOCK" is an undefined clock
Info: Clock "CLOCK" Internal fmax is restricted to 200.0 MHz between source memory "ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0" and destination memory "ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest memory to memory delay is 2.645 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0'
            Info: 2: + IC(0.000 ns) + CELL(2.645 ns) = 2.645 ns; Loc. = M4K_X13_Y1; Fanout = 0; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0'
            Info: Total cell delay = 2.645 ns ( 100.00 % )
        Info: - Smallest clock skew is -0.025 ns
            Info: + Shortest clock path from clock "CLOCK" to destination memory is 2.736 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'CLOCK~clkctrl'
                Info: 3: + IC(0.984 ns) + CELL(0.635 ns) = 2.736 ns; Loc. = M4K_X13_Y1; Fanout = 0; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0'
                Info: Total cell delay = 1.634 ns ( 59.72 % )
                Info: Total interconnect delay = 1.102 ns ( 40.28 % )
            Info: - Longest clock path from clock "CLOCK" to source memory is 2.761 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'CLOCK~clkctrl'
                Info: 3: + IC(0.984 ns) + CELL(0.660 ns) = 2.761 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0'
                Info: Total cell delay = 1.659 ns ( 60.09 % )
                Info: Total interconnect delay = 1.102 ns ( 39.91 % )
        Info: + Micro clock to output delay of source is 0.209 ns
        Info: + Micro setup delay of destination is 0.035 ns
Info: tsu for memory "ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0" (data pin = "ADDR[0]", clock pin = "CLOCK") is 4.002 ns
    Info: + Longest pin to memory delay is 6.729 ns
        Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_AD10; Fanout = 1; PIN Node = 'ADDR[0]'
        Info: 2: + IC(5.747 ns) + CELL(0.142 ns) = 6.729 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0'
        Info: Total cell delay = 0.982 ns ( 14.59 % )
        Info: Total interconnect delay = 5.747 ns ( 85.41 % )
    Info: + Micro setup delay of destination is 0.035 ns
    Info: - Shortest clock path from clock "CLOCK" to destination memory is 2.762 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'CLOCK~clkctrl'
        Info: 3: + IC(0.984 ns) + CELL(0.661 ns) = 2.762 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0'
        Info: Total cell delay = 1.660 ns ( 60.10 % )
        Info: Total interconnect delay = 1.102 ns ( 39.90 % )
Info: tco from clock "CLOCK" to destination pin "DATAOUT[0]" through memory "ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg" is 10.125 ns
    Info: + Longest clock path from clock "CLOCK" to source memory is 2.762 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'CLOCK~clkctrl'
        Info: 3: + IC(0.984 ns) + CELL(0.661 ns) = 2.762 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg'
        Info: Total cell delay = 1.660 ns ( 60.10 % )
        Info: Total interconnect delay = 1.102 ns ( 39.90 % )
    Info: + Micro clock to output delay of source is 0.209 ns
    Info: + Longest memory to pin delay is 7.154 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg'
        Info: 2: + IC(0.000 ns) + CELL(2.993 ns) = 2.993 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[0]'
        Info: 3: + IC(1.382 ns) + CELL(2.779 ns) = 7.154 ns; Loc. = PIN_AA7; Fanout = 0; PIN Node = 'DATAOUT[0]'
        Info: Total cell delay = 5.772 ns ( 80.68 % )
        Info: Total interconnect delay = 1.382 ns ( 19.32 % )
Info: th for memory "ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg" (data pin = "WR", clock pin = "CLOCK") is -0.801 ns
    Info: + Longest clock path from clock "CLOCK" to destination memory is 2.762 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'CLOCK~clkctrl'
        Info: 3: + IC(0.984 ns) + CELL(0.661 ns) = 2.762 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg'
        Info: Total cell delay = 1.660 ns ( 60.10 % )
        Info: Total interconnect delay = 1.102 ns ( 39.90 % )
    Info: + Micro hold delay of destination is 0.234 ns
    Info: - Shortest pin to memory delay is 3.797 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; PIN Node = 'WR'
        Info: 2: + IC(2.509 ns) + CELL(0.309 ns) = 3.797 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg'
        Info: Total cell delay = 1.288 ns ( 33.92 % )
        Info: Total interconnect delay = 2.509 ns ( 66.08 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Jul 31 16:52:54 2007
    Info: Elapsed time: 00:00:01