part1.map.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 10 21:38:36 2008 " "Info: Processing started: Thu Apr 10 21:38:36 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part1 -c part1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part1 -c part1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ramlpm.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ramlpm.v" { { "Info" "ISGN_ENTITY_NAME" "1 ramlpm " "Info: Found entity 1: ramlpm" {  } { { "ramlpm.v" "" { Text "D:/Work/Altera/exercise/lab8/part1/ramlpm.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file part1.v" { { "Info" "ISGN_ENTITY_NAME" "1 part1 " "Info: Found entity 1: part1" {  } { { "part1.v" "" { Text "D:/Work/Altera/exercise/lab8/part1/part1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part1 " "Info: Elaborating entity \"part1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ramlpm ramlpm:u0 " "Info: Elaborating entity \"ramlpm\" for hierarchy \"ramlpm:u0\"" {  } { { "part1.v" "u0" { Text "D:/Work/Altera/exercise/lab8/part1/part1.v" 14 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ramlpm:u0\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"ramlpm:u0\|altsyncram:altsyncram_component\"" {  } { { "ramlpm.v" "altsyncram_component" { Text "D:/Work/Altera/exercise/lab8/part1/ramlpm.v" 71 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "ramlpm:u0\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"ramlpm:u0\|altsyncram:altsyncram_component\"" {  } { { "ramlpm.v" "" { Text "D:/Work/Altera/exercise/lab8/part1/ramlpm.v" 71 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_s8h1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_s8h1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_s8h1 " "Info: Found entity 1: altsyncram_s8h1" {  } { { "db/altsyncram_s8h1.tdf" "" { Text "D:/Work/Altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_s8h1 ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated " "Info: Elaborating entity \"altsyncram_s8h1\" for hierarchy \"ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "31 " "Info: Implemented 31 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "15 " "Info: Implemented 15 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 10 21:38:46 2008 " "Info: Processing ended: Thu Apr 10 21:38:46 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}