part1.tan.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLOCK memory memory ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_datain_reg0 ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_memory_reg0 200.0 MHz Internal " "Info: Clock \"CLOCK\" Internal fmax is restricted to 200.0 MHz between source memory \"ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_datain_reg0\" and destination memory \"ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_memory_reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.645 ns + Longest memory memory " "Info: + Longest memory to memory delay is 2.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_datain_reg0 1 MEM M4K_X13_Y1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.645 ns) 2.645 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_memory_reg0 2 MEM M4K_X13_Y1 0 " "Info: 2: + IC(0.000 ns) + CELL(2.645 ns) = 2.645 ns; Loc. = M4K_X13_Y1; Fanout = 0; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_memory_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.645 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.645 ns ( 100.00 % ) " "Info: Total cell delay = 2.645 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.645 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.645 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 2.645ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.025 ns - Smallest " "Info: - Smallest clock skew is -0.025 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK destination 2.736 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLOCK\" to destination memory is 2.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'CLOCK~clkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK CLOCK~clkctrl } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.635 ns) 2.736 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_memory_reg0 3 MEM M4K_X13_Y1 0 " "Info: 3: + IC(0.984 ns) + CELL(0.635 ns) = 2.736 ns; Loc. = M4K_X13_Y1; Fanout = 0; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_memory_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.619 ns" { CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns ( 59.72 % ) " "Info: Total cell delay = 1.634 ns ( 59.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.102 ns ( 40.28 % ) " "Info: Total interconnect delay = 1.102 ns ( 40.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.736 ns" { CLOCK CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.736 ns" { CLOCK CLOCK~combout CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns 0.118ns 0.984ns } { 0.000ns 0.999ns 0.000ns 0.635ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK source 2.761 ns - Longest memory " "Info: - Longest clock path from clock \"CLOCK\" to source memory is 2.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'CLOCK~clkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK CLOCK~clkctrl } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.660 ns) 2.761 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_datain_reg0 3 MEM M4K_X13_Y1 1 " "Info: 3: + IC(0.984 ns) + CELL(0.660 ns) = 2.761 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.644 ns" { CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.659 ns ( 60.09 % ) " "Info: Total cell delay = 1.659 ns ( 60.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.102 ns ( 39.91 % ) " "Info: Total interconnect delay = 1.102 ns ( 39.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.761 ns" { CLOCK CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.761 ns" { CLOCK CLOCK~combout CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 0.118ns 0.984ns } { 0.000ns 0.999ns 0.000ns 0.660ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.736 ns" { CLOCK CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.736 ns" { CLOCK CLOCK~combout CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns 0.118ns 0.984ns } { 0.000ns 0.999ns 0.000ns 0.635ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.761 ns" { CLOCK CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.761 ns" { CLOCK CLOCK~combout CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 0.118ns 0.984ns } { 0.000ns 0.999ns 0.000ns 0.660ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.645 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.645 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 2.645ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.736 ns" { CLOCK CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.736 ns" { CLOCK CLOCK~combout CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns 0.118ns 0.984ns } { 0.000ns 0.999ns 0.000ns 0.635ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.761 ns" { CLOCK CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.761 ns" { CLOCK CLOCK~combout CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 0.118ns 0.984ns } { 0.000ns 0.999ns 0.000ns 0.660ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } {  } {  } } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_address_reg0 ADDR\[0\] CLOCK 4.002 ns memory " "Info: tsu for memory \"ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_address_reg0\" (data pin = \"ADDR\[0\]\", clock pin = \"CLOCK\") is 4.002 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.729 ns + Longest pin memory " "Info: + Longest pin to memory delay is 6.729 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns ADDR\[0\] 1 PIN PIN_AD10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_AD10; Fanout = 1; PIN Node = 'ADDR\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ADDR[0] } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.747 ns) + CELL(0.142 ns) 6.729 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M4K_X13_Y1 8 " "Info: 2: + IC(5.747 ns) + CELL(0.142 ns) = 6.729 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.889 ns" { ADDR[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.982 ns ( 14.59 % ) " "Info: Total cell delay = 0.982 ns ( 14.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.747 ns ( 85.41 % ) " "Info: Total interconnect delay = 5.747 ns ( 85.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.729 ns" { ADDR[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.729 ns" { ADDR[0] ADDR[0]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 5.747ns } { 0.000ns 0.840ns 0.142ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK destination 2.762 ns - Shortest memory " "Info: - Shortest clock path from clock \"CLOCK\" to destination memory is 2.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'CLOCK~clkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK CLOCK~clkctrl } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.661 ns) 2.762 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_address_reg0 3 MEM M4K_X13_Y1 8 " "Info: 3: + IC(0.984 ns) + CELL(0.661 ns) = 2.762 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.645 ns" { CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 60.10 % ) " "Info: Total cell delay = 1.660 ns ( 60.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.102 ns ( 39.90 % ) " "Info: Total interconnect delay = 1.102 ns ( 39.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.762 ns" { CLOCK CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.762 ns" { CLOCK CLOCK~combout CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.118ns 0.984ns } { 0.000ns 0.999ns 0.000ns 0.661ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.729 ns" { ADDR[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.729 ns" { ADDR[0] ADDR[0]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 5.747ns } { 0.000ns 0.840ns 0.142ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.762 ns" { CLOCK CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.762 ns" { CLOCK CLOCK~combout CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.118ns 0.984ns } { 0.000ns 0.999ns 0.000ns 0.661ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK DATAOUT\[0\] ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg 10.125 ns memory " "Info: tco from clock \"CLOCK\" to destination pin \"DATAOUT\[0\]\" through memory \"ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg\" is 10.125 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK source 2.762 ns + Longest memory " "Info: + Longest clock path from clock \"CLOCK\" to source memory is 2.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'CLOCK~clkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK CLOCK~clkctrl } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.661 ns) 2.762 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg 3 MEM M4K_X13_Y1 8 " "Info: 3: + IC(0.984 ns) + CELL(0.661 ns) = 2.762 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.645 ns" { CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 60.10 % ) " "Info: Total cell delay = 1.660 ns ( 60.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.102 ns ( 39.90 % ) " "Info: Total interconnect delay = 1.102 ns ( 39.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.762 ns" { CLOCK CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.762 ns" { CLOCK CLOCK~combout CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 0.118ns 0.984ns } { 0.000ns 0.999ns 0.000ns 0.661ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.154 ns + Longest memory pin " "Info: + Longest memory to pin delay is 7.154 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg 1 MEM M4K_X13_Y1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.993 ns) 2.993 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|q_a\[0\] 2 MEM M4K_X13_Y1 1 " "Info: 2: + IC(0.000 ns) + CELL(2.993 ns) = 2.993 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|q_a\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.993 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(2.779 ns) 7.154 ns DATAOUT\[0\] 3 PIN PIN_AA7 0 " "Info: 3: + IC(1.382 ns) + CELL(2.779 ns) = 7.154 ns; Loc. = PIN_AA7; Fanout = 0; PIN Node = 'DATAOUT\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.161 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[0] DATAOUT[0] } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.772 ns ( 80.68 % ) " "Info: Total cell delay = 5.772 ns ( 80.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.382 ns ( 19.32 % ) " "Info: Total interconnect delay = 1.382 ns ( 19.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.154 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[0] DATAOUT[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.154 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[0] DATAOUT[0] } { 0.000ns 0.000ns 1.382ns } { 0.000ns 2.993ns 2.779ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.762 ns" { CLOCK CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.762 ns" { CLOCK CLOCK~combout CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 0.118ns 0.984ns } { 0.000ns 0.999ns 0.000ns 0.661ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.154 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[0] DATAOUT[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.154 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[0] DATAOUT[0] } { 0.000ns 0.000ns 1.382ns } { 0.000ns 2.993ns 2.779ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg WR CLOCK -0.801 ns memory " "Info: th for memory \"ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg\" (data pin = \"WR\", clock pin = \"CLOCK\") is -0.801 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK destination 2.762 ns + Longest memory " "Info: + Longest clock path from clock \"CLOCK\" to destination memory is 2.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK~clkctrl 2 COMB CLKCTRL_G3 22 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 22; COMB Node = 'CLOCK~clkctrl'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK CLOCK~clkctrl } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.661 ns) 2.762 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg 3 MEM M4K_X13_Y1 8 " "Info: 3: + IC(0.984 ns) + CELL(0.661 ns) = 2.762 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.645 ns" { CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 60.10 % ) " "Info: Total cell delay = 1.660 ns ( 60.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.102 ns ( 39.90 % ) " "Info: Total interconnect delay = 1.102 ns ( 39.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.762 ns" { CLOCK CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.762 ns" { CLOCK CLOCK~combout CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 0.118ns 0.984ns } { 0.000ns 0.999ns 0.000ns 0.661ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.234 ns + " "Info: + Micro hold delay of destination is 0.234 ns" {  } { { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.797 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 3.797 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns WR 1 PIN PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; PIN Node = 'WR'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "part1.v" "" { Text "F:/altera/exercise/lab8/part1/part1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.509 ns) + CELL(0.309 ns) 3.797 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg 2 MEM M4K_X13_Y1 8 " "Info: 2: + IC(2.509 ns) + CELL(0.309 ns) = 3.797 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.818 ns" { WR ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part1/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.288 ns ( 33.92 % ) " "Info: Total cell delay = 1.288 ns ( 33.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.509 ns ( 66.08 % ) " "Info: Total interconnect delay = 2.509 ns ( 66.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.797 ns" { WR ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.797 ns" { WR WR~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 2.509ns } { 0.000ns 0.979ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.762 ns" { CLOCK CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.762 ns" { CLOCK CLOCK~combout CLOCK~clkctrl ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 0.118ns 0.984ns } { 0.000ns 0.999ns 0.000ns 0.661ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.797 ns" { WR ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.797 ns" { WR WR~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 2.509ns } { 0.000ns 0.979ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}