part1.hier_info

基于FPGA的CPU设计 VHDL 编写

|part1
ADDR[0] => ADDR[0]~4.IN1
ADDR[1] => ADDR[1]~3.IN1
ADDR[2] => ADDR[2]~2.IN1
ADDR[3] => ADDR[3]~1.IN1
ADDR[4] => ADDR[4]~0.IN1
DATAIN[0] => DATAIN[0]~7.IN1
DATAIN[1] => DATAIN[1]~6.IN1
DATAIN[2] => DATAIN[2]~5.IN1
DATAIN[3] => DATAIN[3]~4.IN1
DATAIN[4] => DATAIN[4]~3.IN1
DATAIN[5] => DATAIN[5]~2.IN1
DATAIN[6] => DATAIN[6]~1.IN1
DATAIN[7] => DATAIN[7]~0.IN1
WR => WR~0.IN1
CLOCK => CLOCK~0.IN1
DATAOUT[0] <= ramlpm:u0.q
DATAOUT[1] <= ramlpm:u0.q
DATAOUT[2] <= ramlpm:u0.q
DATAOUT[3] <= ramlpm:u0.q
DATAOUT[4] <= ramlpm:u0.q
DATAOUT[5] <= ramlpm:u0.q
DATAOUT[6] <= ramlpm:u0.q
DATAOUT[7] <= ramlpm:u0.q


|part1|ramlpm:u0
address[0] => address[0]~4.IN1
address[1] => address[1]~3.IN1
address[2] => address[2]~2.IN1
address[3] => address[3]~1.IN1
address[4] => address[4]~0.IN1
clock => clock~0.IN1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
wren => wren~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|part1|ramlpm:u0|altsyncram:altsyncram_component
wren_a => altsyncram_s8h1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_s8h1:auto_generated.data_a[0]
data_a[1] => altsyncram_s8h1:auto_generated.data_a[1]
data_a[2] => altsyncram_s8h1:auto_generated.data_a[2]
data_a[3] => altsyncram_s8h1:auto_generated.data_a[3]
data_a[4] => altsyncram_s8h1:auto_generated.data_a[4]
data_a[5] => altsyncram_s8h1:auto_generated.data_a[5]
data_a[6] => altsyncram_s8h1:auto_generated.data_a[6]
data_a[7] => altsyncram_s8h1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_s8h1:auto_generated.address_a[0]
address_a[1] => altsyncram_s8h1:auto_generated.address_a[1]
address_a[2] => altsyncram_s8h1:auto_generated.address_a[2]
address_a[3] => altsyncram_s8h1:auto_generated.address_a[3]
address_a[4] => altsyncram_s8h1:auto_generated.address_a[4]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_s8h1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_s8h1:auto_generated.q_a[0]
q_a[1] <= altsyncram_s8h1:auto_generated.q_a[1]
q_a[2] <= altsyncram_s8h1:auto_generated.q_a[2]
q_a[3] <= altsyncram_s8h1:auto_generated.q_a[3]
q_a[4] <= altsyncram_s8h1:auto_generated.q_a[4]
q_a[5] <= altsyncram_s8h1:auto_generated.q_a[5]
q_a[6] <= altsyncram_s8h1:auto_generated.q_a[6]
q_a[7] <= altsyncram_s8h1:auto_generated.q_a[7]
q_b[0] <= <GND>


|part1|ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE