part1.tan.summary

基于FPGA的CPU设计 VHDL 编写

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.002 ns
From           : ADDR[0]
To             : ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0
From Clock     : --
To Clock       : CLOCK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.125 ns
From           : ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4
To             : DATAOUT[0]
From Clock     : CLOCK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.801 ns
From           : WR
To             : ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg
From Clock     : --
To Clock       : CLOCK
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 200.00 MHz ( period = 5.000 ns )
From           : ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg7
To             : ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a7~porta_memory_reg0
From Clock     : CLOCK
To Clock       : CLOCK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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