📄 part1.map.rpt
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; -- 4 input functions ; 0 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 0 ;
; -- Combinational cells for routing ; 0 ;
; Logic elements by mode ; ;
; -- normal mode ; 0 ;
; -- arithmetic mode ; 0 ;
; Total registers ; 0 ;
; I/O pins ; 23 ;
; Total memory bits ; 256 ;
; Maximum fan-out node ; WR ;
; Maximum fan-out ; 8 ;
; Total fan-out ; 72 ;
; Average fan-out ; 2.32 ;
+---------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+-------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------+
; |part1 ; 0 (0) ; 0 (0) ; 256 ; 8 ; 0 ; 0 ; 0 ; 23 ; 0 ; |part1 ;
; |ramlpm:u0| ; 0 (0) ; 0 (0) ; 256 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part1|ramlpm:u0 ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 256 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part1|ramlpm:u0|altsyncram:altsyncram_component ;
; |altsyncram_s8h1:auto_generated| ; 0 (0) ; 0 (0) ; 256 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; |part1|ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated ;
+-------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------+
; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ALTSYNCRAM ; M4K ; Single Port ; 32 ; 8 ; -- ; -- ; 256 ; None ;
+-------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------+
; Source assignments for ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------+
+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ramlpm:u0|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+---------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+-----------------+---------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; SINGLE_PORT ; Untyped ;
; WIDTH_A ; 8 ; Integer ;
; WIDTHAD_A ; 5 ; Integer ;
; NUMWORDS_A ; 32 ; Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; M4K ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CBXI_PARAMETER ; altsyncram_s8h1 ; Untyped ;
+------------------------------------+-----------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Apr 10 21:38:36 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part1 -c part1
Info: Found 1 design units, including 1 entities, in source file ramlpm.v
Info: Found entity 1: ramlpm
Info: Found 1 design units, including 1 entities, in source file part1.v
Info: Found entity 1: part1
Info: Elaborating entity "part1" for the top level hierarchy
Info: Elaborating entity "ramlpm" for hierarchy "ramlpm:u0"
Info: Found 1 design units, including 1 entities, in source file ../../../../../program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "ramlpm:u0|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "ramlpm:u0|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_s8h1.tdf
Info: Found entity 1: altsyncram_s8h1
Info: Elaborating entity "altsyncram_s8h1" for hierarchy "ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated"
Info: Implemented 31 device resources after synthesis - the final resource count might be different
Info: Implemented 15 input pins
Info: Implemented 8 output pins
Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Thu Apr 10 21:38:46 2008
Info: Elapsed time: 00:00:10
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