part1.fit.eqn

基于FPGA的CPU设计 VHDL 编写

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--D1_q_a[0] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[0] at M4K_X26_Y35
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 8
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[0]_PORT_A_data_in = BUS(DATAIN[0], DATAIN[1], DATAIN[2], DATAIN[3], DATAIN[4], DATAIN[5], DATAIN[6], DATAIN[7]);
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = WR;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = GLOBAL(A1L8);
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, , D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[0] = D1_q_a[0]_PORT_A_data_out[0];

--D1_q_a[7] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[7] at M4K_X26_Y35
D1_q_a[0]_PORT_A_data_in = BUS(DATAIN[0], DATAIN[1], DATAIN[2], DATAIN[3], DATAIN[4], DATAIN[5], DATAIN[6], DATAIN[7]);
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = WR;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = GLOBAL(A1L8);
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, , D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[7] = D1_q_a[0]_PORT_A_data_out[7];

--D1_q_a[6] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[6] at M4K_X26_Y35
D1_q_a[0]_PORT_A_data_in = BUS(DATAIN[0], DATAIN[1], DATAIN[2], DATAIN[3], DATAIN[4], DATAIN[5], DATAIN[6], DATAIN[7]);
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = WR;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = GLOBAL(A1L8);
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, , D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[6] = D1_q_a[0]_PORT_A_data_out[6];

--D1_q_a[5] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[5] at M4K_X26_Y35
D1_q_a[0]_PORT_A_data_in = BUS(DATAIN[0], DATAIN[1], DATAIN[2], DATAIN[3], DATAIN[4], DATAIN[5], DATAIN[6], DATAIN[7]);
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = WR;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = GLOBAL(A1L8);
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, , D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[5] = D1_q_a[0]_PORT_A_data_out[5];

--D1_q_a[4] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[4] at M4K_X26_Y35
D1_q_a[0]_PORT_A_data_in = BUS(DATAIN[0], DATAIN[1], DATAIN[2], DATAIN[3], DATAIN[4], DATAIN[5], DATAIN[6], DATAIN[7]);
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = WR;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = GLOBAL(A1L8);
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, , D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[4] = D1_q_a[0]_PORT_A_data_out[4];

--D1_q_a[3] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[3] at M4K_X26_Y35
D1_q_a[0]_PORT_A_data_in = BUS(DATAIN[0], DATAIN[1], DATAIN[2], DATAIN[3], DATAIN[4], DATAIN[5], DATAIN[6], DATAIN[7]);
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = WR;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = GLOBAL(A1L8);
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, , D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[3] = D1_q_a[0]_PORT_A_data_out[3];

--D1_q_a[2] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[2] at M4K_X26_Y35
D1_q_a[0]_PORT_A_data_in = BUS(DATAIN[0], DATAIN[1], DATAIN[2], DATAIN[3], DATAIN[4], DATAIN[5], DATAIN[6], DATAIN[7]);
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = WR;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = GLOBAL(A1L8);
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, , D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[2] = D1_q_a[0]_PORT_A_data_out[2];

--D1_q_a[1] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[1] at M4K_X26_Y35
D1_q_a[0]_PORT_A_data_in = BUS(DATAIN[0], DATAIN[1], DATAIN[2], DATAIN[3], DATAIN[4], DATAIN[5], DATAIN[6], DATAIN[7]);
D1_q_a[0]_PORT_A_data_in_reg = DFFE(D1_q_a[0]_PORT_A_data_in, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_address = BUS(ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4]);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_PORT_A_write_enable = WR;
D1_q_a[0]_PORT_A_write_enable_reg = DFFE(D1_q_a[0]_PORT_A_write_enable, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = GLOBAL(A1L8);
D1_q_a[0]_PORT_A_data_out = MEMORY(D1_q_a[0]_PORT_A_data_in_reg, , D1_q_a[0]_PORT_A_address_reg, , D1_q_a[0]_PORT_A_write_enable_reg, , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[1] = D1_q_a[0]_PORT_A_data_out[1];


--WR is WR at PIN_C13
--operation mode is input

WR = INPUT();


--CLOCK is CLOCK at PIN_P2
--operation mode is input

CLOCK = INPUT();


--DATAIN[0] is DATAIN[0] at PIN_D13
--operation mode is input

DATAIN[0] = INPUT();


--ADDR[0] is ADDR[0] at PIN_F13
--operation mode is input

ADDR[0] = INPUT();


--ADDR[1] is ADDR[1] at PIN_D14
--operation mode is input

ADDR[1] = INPUT();


--ADDR[2] is ADDR[2] at PIN_E18
--operation mode is input

ADDR[2] = INPUT();


--ADDR[3] is ADDR[3] at PIN_B16
--operation mode is input

ADDR[3] = INPUT();


--ADDR[4] is ADDR[4] at PIN_C12
--operation mode is input

ADDR[4] = INPUT();


--DATAIN[1] is DATAIN[1] at PIN_G13
--operation mode is input

DATAIN[1] = INPUT();


--DATAIN[2] is DATAIN[2] at PIN_J10
--operation mode is input

DATAIN[2] = INPUT();


--DATAIN[3] is DATAIN[3] at PIN_J11
--operation mode is input

DATAIN[3] = INPUT();


--DATAIN[4] is DATAIN[4] at PIN_B3
--operation mode is input

DATAIN[4] = INPUT();


--DATAIN[5] is DATAIN[5] at PIN_A14
--operation mode is input

DATAIN[5] = INPUT();


--DATAIN[6] is DATAIN[6] at PIN_C16
--operation mode is input

DATAIN[6] = INPUT();


--DATAIN[7] is DATAIN[7] at PIN_G11
--operation mode is input

DATAIN[7] = INPUT();


--DATAOUT[0] is DATAOUT[0] at PIN_D11
--operation mode is output

DATAOUT[0] = OUTPUT(D1_q_a[0]);


--DATAOUT[1] is DATAOUT[1] at PIN_C10
--operation mode is output

DATAOUT[1] = OUTPUT(D1_q_a[1]);


--DATAOUT[2] is DATAOUT[2] at PIN_J14
--operation mode is output

DATAOUT[2] = OUTPUT(D1_q_a[2]);


--DATAOUT[3] is DATAOUT[3] at PIN_B12
--operation mode is output

DATAOUT[3] = OUTPUT(D1_q_a[3]);


--DATAOUT[4] is DATAOUT[4] at PIN_D16
--operation mode is output

DATAOUT[4] = OUTPUT(D1_q_a[4]);


--DATAOUT[5] is DATAOUT[5] at PIN_D10
--operation mode is output

DATAOUT[5] = OUTPUT(D1_q_a[5]);


--DATAOUT[6] is DATAOUT[6] at PIN_J13
--operation mode is output

DATAOUT[6] = OUTPUT(D1_q_a[6]);


--DATAOUT[7] is DATAOUT[7] at PIN_E5
--operation mode is output

DATAOUT[7] = OUTPUT(D1_q_a[7]);





--A1L8 is CLOCK~clkctrl at CLKCTRL_G3
A1L8 = cycloneii_clkctrl(.INCLK[0] = CLOCK) WITH (clock_type = "Global Clock");