part1.map.summary

基于FPGA的CPU设计 VHDL 编写

Analysis & Synthesis Status : Successful - Thu Apr 10 21:38:46 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : part1
Top-level Entity Name : part1
Family : Cyclone II
Total logic elements : 0
Total registers : 0
Total pins : 23
Total virtual pins : 0
Total memory bits : 256
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0