📄 part6.map.eqn
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--J1_q_a[6] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
J1_q_a[6]_PORT_A_data_in = SW[6];
J1_q_a[6]_PORT_A_data_in_reg = DFFE(J1_q_a[6]_PORT_A_data_in, J1_q_a[6]_clock_0, , , );
J1_q_a[6]_PORT_B_data_in = H1_ram_rom_data_reg[6];
J1_q_a[6]_PORT_B_data_in_reg = DFFE(J1_q_a[6]_PORT_B_data_in, J1_q_a[6]_clock_1, , , );
J1_q_a[6]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[6]_PORT_A_address_reg = DFFE(J1_q_a[6]_PORT_A_address, J1_q_a[6]_clock_0, , , );
J1_q_a[6]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[6]_PORT_B_address_reg = DFFE(J1_q_a[6]_PORT_B_address, J1_q_a[6]_clock_1, , , );
J1_q_a[6]_PORT_A_write_enable = SW[17];
J1_q_a[6]_PORT_A_write_enable_reg = DFFE(J1_q_a[6]_PORT_A_write_enable, J1_q_a[6]_clock_0, , , );
J1_q_a[6]_PORT_B_write_enable = H1L3;
J1_q_a[6]_PORT_B_write_enable_reg = DFFE(J1_q_a[6]_PORT_B_write_enable, J1_q_a[6]_clock_1, , , );
J1_q_a[6]_clock_0 = CLOCK_50;
J1_q_a[6]_clock_1 = A1L110;
J1_q_a[6]_PORT_A_data_out = MEMORY(J1_q_a[6]_PORT_A_data_in_reg, J1_q_a[6]_PORT_B_data_in_reg, J1_q_a[6]_PORT_A_address_reg, J1_q_a[6]_PORT_B_address_reg, J1_q_a[6]_PORT_A_write_enable_reg, J1_q_a[6]_PORT_B_write_enable_reg, , , J1_q_a[6]_clock_0, J1_q_a[6]_clock_1, , , , );
J1_q_a[6] = J1_q_a[6]_PORT_A_data_out[0];
--J1_q_b[6] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[6]
J1_q_b[6]_PORT_A_data_in = SW[6];
J1_q_b[6]_PORT_A_data_in_reg = DFFE(J1_q_b[6]_PORT_A_data_in, J1_q_b[6]_clock_0, , , );
J1_q_b[6]_PORT_B_data_in = H1_ram_rom_data_reg[6];
J1_q_b[6]_PORT_B_data_in_reg = DFFE(J1_q_b[6]_PORT_B_data_in, J1_q_b[6]_clock_1, , , );
J1_q_b[6]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[6]_PORT_A_address_reg = DFFE(J1_q_b[6]_PORT_A_address, J1_q_b[6]_clock_0, , , );
J1_q_b[6]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[6]_PORT_B_address_reg = DFFE(J1_q_b[6]_PORT_B_address, J1_q_b[6]_clock_1, , , );
J1_q_b[6]_PORT_A_write_enable = SW[17];
J1_q_b[6]_PORT_A_write_enable_reg = DFFE(J1_q_b[6]_PORT_A_write_enable, J1_q_b[6]_clock_0, , , );
J1_q_b[6]_PORT_B_write_enable = H1L3;
J1_q_b[6]_PORT_B_write_enable_reg = DFFE(J1_q_b[6]_PORT_B_write_enable, J1_q_b[6]_clock_1, , , );
J1_q_b[6]_clock_0 = CLOCK_50;
J1_q_b[6]_clock_1 = A1L110;
J1_q_b[6]_PORT_B_data_out = MEMORY(J1_q_b[6]_PORT_A_data_in_reg, J1_q_b[6]_PORT_B_data_in_reg, J1_q_b[6]_PORT_A_address_reg, J1_q_b[6]_PORT_B_address_reg, J1_q_b[6]_PORT_A_write_enable_reg, J1_q_b[6]_PORT_B_write_enable_reg, , , J1_q_b[6]_clock_0, J1_q_b[6]_clock_1, , , , );
J1_q_b[6] = J1_q_b[6]_PORT_B_data_out[0];
--J1_q_a[7] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
J1_q_a[7]_PORT_A_data_in = SW[7];
J1_q_a[7]_PORT_A_data_in_reg = DFFE(J1_q_a[7]_PORT_A_data_in, J1_q_a[7]_clock_0, , , );
J1_q_a[7]_PORT_B_data_in = H1_ram_rom_data_reg[7];
J1_q_a[7]_PORT_B_data_in_reg = DFFE(J1_q_a[7]_PORT_B_data_in, J1_q_a[7]_clock_1, , , );
J1_q_a[7]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[7]_PORT_A_address_reg = DFFE(J1_q_a[7]_PORT_A_address, J1_q_a[7]_clock_0, , , );
J1_q_a[7]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[7]_PORT_B_address_reg = DFFE(J1_q_a[7]_PORT_B_address, J1_q_a[7]_clock_1, , , );
J1_q_a[7]_PORT_A_write_enable = SW[17];
J1_q_a[7]_PORT_A_write_enable_reg = DFFE(J1_q_a[7]_PORT_A_write_enable, J1_q_a[7]_clock_0, , , );
J1_q_a[7]_PORT_B_write_enable = H1L3;
J1_q_a[7]_PORT_B_write_enable_reg = DFFE(J1_q_a[7]_PORT_B_write_enable, J1_q_a[7]_clock_1, , , );
J1_q_a[7]_clock_0 = CLOCK_50;
J1_q_a[7]_clock_1 = A1L110;
J1_q_a[7]_PORT_A_data_out = MEMORY(J1_q_a[7]_PORT_A_data_in_reg, J1_q_a[7]_PORT_B_data_in_reg, J1_q_a[7]_PORT_A_address_reg, J1_q_a[7]_PORT_B_address_reg, J1_q_a[7]_PORT_A_write_enable_reg, J1_q_a[7]_PORT_B_write_enable_reg, , , J1_q_a[7]_clock_0, J1_q_a[7]_clock_1, , , , );
J1_q_a[7] = J1_q_a[7]_PORT_A_data_out[0];
--J1_q_b[7] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[7]
J1_q_b[7]_PORT_A_data_in = SW[7];
J1_q_b[7]_PORT_A_data_in_reg = DFFE(J1_q_b[7]_PORT_A_data_in, J1_q_b[7]_clock_0, , , );
J1_q_b[7]_PORT_B_data_in = H1_ram_rom_data_reg[7];
J1_q_b[7]_PORT_B_data_in_reg = DFFE(J1_q_b[7]_PORT_B_data_in, J1_q_b[7]_clock_1, , , );
J1_q_b[7]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[7]_PORT_A_address_reg = DFFE(J1_q_b[7]_PORT_A_address, J1_q_b[7]_clock_0, , , );
J1_q_b[7]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[7]_PORT_B_address_reg = DFFE(J1_q_b[7]_PORT_B_address, J1_q_b[7]_clock_1, , , );
J1_q_b[7]_PORT_A_write_enable = SW[17];
J1_q_b[7]_PORT_A_write_enable_reg = DFFE(J1_q_b[7]_PORT_A_write_enable, J1_q_b[7]_clock_0, , , );
J1_q_b[7]_PORT_B_write_enable = H1L3;
J1_q_b[7]_PORT_B_write_enable_reg = DFFE(J1_q_b[7]_PORT_B_write_enable, J1_q_b[7]_clock_1, , , );
J1_q_b[7]_clock_0 = CLOCK_50;
J1_q_b[7]_clock_1 = A1L110;
J1_q_b[7]_PORT_B_data_out = MEMORY(J1_q_b[7]_PORT_A_data_in_reg, J1_q_b[7]_PORT_B_data_in_reg, J1_q_b[7]_PORT_A_address_reg, J1_q_b[7]_PORT_B_address_reg, J1_q_b[7]_PORT_A_write_enable_reg, J1_q_b[7]_PORT_B_write_enable_reg, , , J1_q_b[7]_clock_0, J1_q_b[7]_clock_1, , , , );
J1_q_b[7] = J1_q_b[7]_PORT_B_data_out[0];
--D1L1 is SEG7_LUT:u1|oSEG[0]~70
D1L1 = J1_q_a[6] & !J1_q_a[5] & (J1_q_a[4] $ !J1_q_a[7]) # !J1_q_a[6] & J1_q_a[4] & (J1_q_a[5] $ !J1_q_a[7]);
--D1L2 is SEG7_LUT:u1|oSEG[1]~71
D1L2 = J1_q_a[5] & (J1_q_a[4] & (J1_q_a[7]) # !J1_q_a[4] & J1_q_a[6]) # !J1_q_a[5] & J1_q_a[6] & (J1_q_a[4] $ J1_q_a[7]);
--D1L3 is SEG7_LUT:u1|oSEG[2]~72
D1L3 = J1_q_a[6] & J1_q_a[7] & (J1_q_a[5] # !J1_q_a[4]) # !J1_q_a[6] & !J1_q_a[4] & J1_q_a[5] & !J1_q_a[7];
--D1L4 is SEG7_LUT:u1|oSEG[3]~73
D1L4 = J1_q_a[4] & (J1_q_a[5] $ !J1_q_a[6]) # !J1_q_a[4] & (J1_q_a[5] & !J1_q_a[6] & J1_q_a[7] # !J1_q_a[5] & J1_q_a[6] & !J1_q_a[7]);
--D1L5 is SEG7_LUT:u1|oSEG[4]~74
D1L5 = J1_q_a[5] & J1_q_a[4] & (!J1_q_a[7]) # !J1_q_a[5] & (J1_q_a[6] & (!J1_q_a[7]) # !J1_q_a[6] & J1_q_a[4]);
--D1L6 is SEG7_LUT:u1|oSEG[5]~75
D1L6 = J1_q_a[4] & (J1_q_a[7] $ (J1_q_a[5] # !J1_q_a[6])) # !J1_q_a[4] & J1_q_a[5] & !J1_q_a[6] & !J1_q_a[7];
--D1L7 is SEG7_LUT:u1|oSEG[6]~76
D1L7 = J1_q_a[4] & (J1_q_a[7] # J1_q_a[5] $ J1_q_a[6]) # !J1_q_a[4] & (J1_q_a[5] # J1_q_a[6] $ J1_q_a[7]);
--read_addr[0] is read_addr[0]
read_addr[0] = DFFEAS(A1L200, CLOCK_50, KEY[0], , A1L86, , , , );
--read_addr[1] is read_addr[1]
read_addr[1] = DFFEAS(A1L203, CLOCK_50, KEY[0], , A1L86, , , , );
--read_addr[2] is read_addr[2]
read_addr[2] = DFFEAS(A1L206, CLOCK_50, KEY[0], , A1L86, , , , );
--read_addr[3] is read_addr[3]
read_addr[3] = DFFEAS(A1L209, CLOCK_50, KEY[0], , A1L86, , , , );
--D4L1 is SEG7_LUT:u4|oSEG[0]~70
D4L1 = read_addr[2] & !read_addr[1] & (read_addr[0] $ !read_addr[3]) # !read_addr[2] & read_addr[0] & (read_addr[1] $ !read_addr[3]);
--D4L2 is SEG7_LUT:u4|oSEG[1]~71
D4L2 = read_addr[1] & (read_addr[0] & (read_addr[3]) # !read_addr[0] & read_addr[2]) # !read_addr[1] & read_addr[2] & (read_addr[0] $ read_addr[3]);
--D4L3 is SEG7_LUT:u4|oSEG[2]~72
D4L3 = read_addr[2] & read_addr[3] & (read_addr[1] # !read_addr[0]) # !read_addr[2] & !read_addr[0] & read_addr[1] & !read_addr[3];
--D4L4 is SEG7_LUT:u4|oSEG[3]~73
D4L4 = read_addr[0] & (read_addr[1] $ !read_addr[2]) # !read_addr[0] & (read_addr[1] & !read_addr[2] & read_addr[3] # !read_addr[1] & read_addr[2] & !read_addr[3]);
--D4L5 is SEG7_LUT:u4|oSEG[4]~74
D4L5 = read_addr[1] & read_addr[0] & (!read_addr[3]) # !read_addr[1] & (read_addr[2] & (!read_addr[3]) # !read_addr[2] & read_addr[0]);
--D4L6 is SEG7_LUT:u4|oSEG[5]~75
D4L6 = read_addr[0] & (read_addr[3] $ (read_addr[1] # !read_addr[2])) # !read_addr[0] & read_addr[1] & !read_addr[2] & !read_addr[3];
--D4L7 is SEG7_LUT:u4|oSEG[6]~76
D4L7 = read_addr[0] & (read_addr[3] # read_addr[1] $ read_addr[2]) # !read_addr[0] & (read_addr[1] # read_addr[2] $ read_addr[3]);
--read_addr[4] is read_addr[4]
read_addr[4] = DFFEAS(A1L212, CLOCK_50, KEY[0], , A1L86, , , , );
--D6L1 is SEG7_LUT:u6|oSEG[0]~70
D6L1 = SW[2] & !SW[1] & (SW[0] $ !SW[3]) # !SW[2] & SW[0] & (SW[1] $ !SW[3]);
--D6L2 is SEG7_LUT:u6|oSEG[1]~71
D6L2 = SW[1] & (SW[0] & (SW[3]) # !SW[0] & SW[2]) # !SW[1] & SW[2] & (SW[0] $ SW[3]);
--D6L3 is SEG7_LUT:u6|oSEG[2]~72
D6L3 = SW[2] & SW[3] & (SW[1] # !SW[0]) # !SW[2] & !SW[0] & SW[1] & !SW[3];
--D6L4 is SEG7_LUT:u6|oSEG[3]~73
D6L4 = SW[0] & (SW[1] $ !SW[2]) # !SW[0] & (SW[1] & !SW[2] & SW[3] # !SW[1] & SW[2] & !SW[3]);
--D6L5 is SEG7_LUT:u6|oSEG[4]~74
D6L5 = SW[1] & SW[0] & (!SW[3]) # !SW[1] & (SW[2] & (!SW[3]) # !SW[2] & SW[0]);
--D6L6 is SEG7_LUT:u6|oSEG[5]~75
D6L6 = SW[0] & (SW[3] $ (SW[1] # !SW[2])) # !SW[0] & SW[1] & !SW[2] & !SW[3];
--D6L7 is SEG7_LUT:u6|oSEG[6]~76
D6L7 = SW[0] & (SW[3] # SW[1] $ SW[2]) # !SW[0] & (SW[1] # SW[2] $ SW[3]);
--D5L1 is SEG7_LUT:u5|oSEG[0]~70
D5L1 = SW[6] & !SW[5] & (SW[4] $ !SW[7]) # !SW[6] & SW[4] & (SW[5] $ !SW[7]);
--D5L2 is SEG7_LUT:u5|oSEG[1]~71
D5L2 = SW[5] & (SW[4] & (SW[7]) # !SW[4] & SW[6]) # !SW[5] & SW[6] & (SW[4] $ SW[7]);
--D5L3 is SEG7_LUT:u5|oSEG[2]~72
D5L3 = SW[6] & SW[7] & (SW[5] # !SW[4]) # !SW[6] & !SW[4] & SW[5] & !SW[7];
--D5L4 is SEG7_LUT:u5|oSEG[3]~73
D5L4 = SW[4] & (SW[5] $ !SW[6]) # !SW[4] & (SW[5] & !SW[6] & SW[7] # !SW[5] & SW[6] & !SW[7]);
--D5L5 is SEG7_LUT:u5|oSEG[4]~74
D5L5 = SW[5] & SW[4] & (!SW[7]) # !SW[5] & (SW[6] & (!SW[7]) # !SW[6] & SW[4]);
--D5L6 is SEG7_LUT:u5|oSEG[5]~75
D5L6 = SW[4] & (SW[7] $ (SW[5] # !SW[6])) # !SW[4] & SW[5] & !SW[6] & !SW[7];
--D5L7 is SEG7_LUT:u5|oSEG[6]~76
D5L7 = SW[4] & (SW[7] # SW[5] $ SW[6]) # !SW[4] & (SW[5] # SW[6] $ SW[7]);
--D8L1 is SEG7_LUT:u8|oSEG[0]~70
D8L1 = SW[13] & !SW[12] & (SW[11] $ !SW[14]) # !SW[13] & SW[11] & (SW[12] $ !SW[14]);
--D8L2 is SEG7_LUT:u8|oSEG[1]~71
D8L2 = SW[12] & (SW[11] & (SW[14]) # !SW[11] & SW[13]) # !SW[12] & SW[13] & (SW[11] $ SW[14]);
--D8L3 is SEG7_LUT:u8|oSEG[2]~72
D8L3 = SW[13] & SW[14] & (SW[12] # !SW[11]) # !SW[13] & !SW[11] & SW[12] & !SW[14];
--D8L4 is SEG7_LUT:u8|oSEG[3]~73
D8L4 = SW[11] & (SW[12] $ !SW[13]) # !SW[11] & (SW[12] & !SW[13] & SW[14] # !SW[12] & SW[13] & !SW[14]);
--D8L5 is SEG7_LUT:u8|oSEG[4]~74
D8L5 = SW[12] & SW[11] & (!SW[14]) # !SW[12] & (SW[13] & (!SW[14]) # !SW[13] & SW[11]);
--D8L6 is SEG7_LUT:u8|oSEG[5]~75
D8L6 = SW[11] & (SW[14] $ (SW[12] # !SW[13])) # !SW[11] & SW[12] & !SW[13] & !SW[14];
--D8L7 is SEG7_LUT:u8|oSEG[6]~76
D8L7 = SW[11] & (SW[14] # SW[12] $ SW[13]) # !SW[11] & (SW[12] # SW[13] $ SW[14]);
--A1L111 is altera_internal_jtag~TDO
A1L111 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);
--A1L112 is altera_internal_jtag~TMSUTAP
A1L112 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);
--A1L110 is altera_internal_jtag~TCKUTAP
A1L110 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);
--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , C1L19);
--P1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
P1_state[5] = AMPP_FUNCTION(A1L110, P1L22);
--L4_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]
L4_Q[2] = AMPP_FUNCTION(A1L110, C1L22, C1_CLRN_SIGNAL, C1L28);
--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode
C1_jtag_debug_mode = AMPP_FUNCTION(A1L110, C1L39, P1_state[0]);
--L6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
L6_Q[0] = AMPP_FUNCTION(A1L110, altera_internal_jtag, C1_CLRN_SIGNAL, C1L25);
--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L110, A1L214, P1_state[0], P1_state[12]);
--L2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
L2_Q[0] = AMPP_FUNCTION(A1L110, L2L4, C1_CLRN_SIGNAL);
--H1L11 is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33
H1L11 = AMPP_FUNCTION(C1_jtag_debug_mode, L6_Q[0], C1_jtag_debug_mode_usr1, L2_Q[0]);
--H1L3 is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11
H1L3 = AMPP_FUNCTION(P1_state[5], L4_Q[2], H1L11);
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