part6.map.eqn

基于FPGA的CPU设计 VHDL 编写

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--J1_q_a[0] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
J1_q_a[0]_PORT_A_data_in = SW[0];
J1_q_a[0]_PORT_A_data_in_reg = DFFE(J1_q_a[0]_PORT_A_data_in, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_data_in = H1_ram_rom_data_reg[0];
J1_q_a[0]_PORT_B_data_in_reg = DFFE(J1_q_a[0]_PORT_B_data_in, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[0]_PORT_B_address_reg = DFFE(J1_q_a[0]_PORT_B_address, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_write_enable = SW[17];
J1_q_a[0]_PORT_A_write_enable_reg = DFFE(J1_q_a[0]_PORT_A_write_enable, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_write_enable = H1L3;
J1_q_a[0]_PORT_B_write_enable_reg = DFFE(J1_q_a[0]_PORT_B_write_enable, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_clock_0 = CLOCK_50;
J1_q_a[0]_clock_1 = A1L110;
J1_q_a[0]_PORT_A_data_out = MEMORY(J1_q_a[0]_PORT_A_data_in_reg, J1_q_a[0]_PORT_B_data_in_reg, J1_q_a[0]_PORT_A_address_reg, J1_q_a[0]_PORT_B_address_reg, J1_q_a[0]_PORT_A_write_enable_reg, J1_q_a[0]_PORT_B_write_enable_reg, , , J1_q_a[0]_clock_0, J1_q_a[0]_clock_1, , , , );
J1_q_a[0] = J1_q_a[0]_PORT_A_data_out[0];

--J1_q_b[0] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[0]
J1_q_b[0]_PORT_A_data_in = SW[0];
J1_q_b[0]_PORT_A_data_in_reg = DFFE(J1_q_b[0]_PORT_A_data_in, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_data_in = H1_ram_rom_data_reg[0];
J1_q_b[0]_PORT_B_data_in_reg = DFFE(J1_q_b[0]_PORT_B_data_in, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[0]_PORT_A_address_reg = DFFE(J1_q_b[0]_PORT_A_address, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[0]_PORT_B_address_reg = DFFE(J1_q_b[0]_PORT_B_address, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_write_enable = SW[17];
J1_q_b[0]_PORT_A_write_enable_reg = DFFE(J1_q_b[0]_PORT_A_write_enable, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_write_enable = H1L3;
J1_q_b[0]_PORT_B_write_enable_reg = DFFE(J1_q_b[0]_PORT_B_write_enable, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_clock_0 = CLOCK_50;
J1_q_b[0]_clock_1 = A1L110;
J1_q_b[0]_PORT_B_data_out = MEMORY(J1_q_b[0]_PORT_A_data_in_reg, J1_q_b[0]_PORT_B_data_in_reg, J1_q_b[0]_PORT_A_address_reg, J1_q_b[0]_PORT_B_address_reg, J1_q_b[0]_PORT_A_write_enable_reg, J1_q_b[0]_PORT_B_write_enable_reg, , , J1_q_b[0]_clock_0, J1_q_b[0]_clock_1, , , , );
J1_q_b[0] = J1_q_b[0]_PORT_B_data_out[0];


--J1_q_a[1] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
J1_q_a[1]_PORT_A_data_in = SW[1];
J1_q_a[1]_PORT_A_data_in_reg = DFFE(J1_q_a[1]_PORT_A_data_in, J1_q_a[1]_clock_0, , , );
J1_q_a[1]_PORT_B_data_in = H1_ram_rom_data_reg[1];
J1_q_a[1]_PORT_B_data_in_reg = DFFE(J1_q_a[1]_PORT_B_data_in, J1_q_a[1]_clock_1, , , );
J1_q_a[1]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[1]_PORT_A_address_reg = DFFE(J1_q_a[1]_PORT_A_address, J1_q_a[1]_clock_0, , , );
J1_q_a[1]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[1]_PORT_B_address_reg = DFFE(J1_q_a[1]_PORT_B_address, J1_q_a[1]_clock_1, , , );
J1_q_a[1]_PORT_A_write_enable = SW[17];
J1_q_a[1]_PORT_A_write_enable_reg = DFFE(J1_q_a[1]_PORT_A_write_enable, J1_q_a[1]_clock_0, , , );
J1_q_a[1]_PORT_B_write_enable = H1L3;
J1_q_a[1]_PORT_B_write_enable_reg = DFFE(J1_q_a[1]_PORT_B_write_enable, J1_q_a[1]_clock_1, , , );
J1_q_a[1]_clock_0 = CLOCK_50;
J1_q_a[1]_clock_1 = A1L110;
J1_q_a[1]_PORT_A_data_out = MEMORY(J1_q_a[1]_PORT_A_data_in_reg, J1_q_a[1]_PORT_B_data_in_reg, J1_q_a[1]_PORT_A_address_reg, J1_q_a[1]_PORT_B_address_reg, J1_q_a[1]_PORT_A_write_enable_reg, J1_q_a[1]_PORT_B_write_enable_reg, , , J1_q_a[1]_clock_0, J1_q_a[1]_clock_1, , , , );
J1_q_a[1] = J1_q_a[1]_PORT_A_data_out[0];

--J1_q_b[1] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[1]
J1_q_b[1]_PORT_A_data_in = SW[1];
J1_q_b[1]_PORT_A_data_in_reg = DFFE(J1_q_b[1]_PORT_A_data_in, J1_q_b[1]_clock_0, , , );
J1_q_b[1]_PORT_B_data_in = H1_ram_rom_data_reg[1];
J1_q_b[1]_PORT_B_data_in_reg = DFFE(J1_q_b[1]_PORT_B_data_in, J1_q_b[1]_clock_1, , , );
J1_q_b[1]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[1]_PORT_A_address_reg = DFFE(J1_q_b[1]_PORT_A_address, J1_q_b[1]_clock_0, , , );
J1_q_b[1]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[1]_PORT_B_address_reg = DFFE(J1_q_b[1]_PORT_B_address, J1_q_b[1]_clock_1, , , );
J1_q_b[1]_PORT_A_write_enable = SW[17];
J1_q_b[1]_PORT_A_write_enable_reg = DFFE(J1_q_b[1]_PORT_A_write_enable, J1_q_b[1]_clock_0, , , );
J1_q_b[1]_PORT_B_write_enable = H1L3;
J1_q_b[1]_PORT_B_write_enable_reg = DFFE(J1_q_b[1]_PORT_B_write_enable, J1_q_b[1]_clock_1, , , );
J1_q_b[1]_clock_0 = CLOCK_50;
J1_q_b[1]_clock_1 = A1L110;
J1_q_b[1]_PORT_B_data_out = MEMORY(J1_q_b[1]_PORT_A_data_in_reg, J1_q_b[1]_PORT_B_data_in_reg, J1_q_b[1]_PORT_A_address_reg, J1_q_b[1]_PORT_B_address_reg, J1_q_b[1]_PORT_A_write_enable_reg, J1_q_b[1]_PORT_B_write_enable_reg, , , J1_q_b[1]_clock_0, J1_q_b[1]_clock_1, , , , );
J1_q_b[1] = J1_q_b[1]_PORT_B_data_out[0];


--J1_q_a[2] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
J1_q_a[2]_PORT_A_data_in = SW[2];
J1_q_a[2]_PORT_A_data_in_reg = DFFE(J1_q_a[2]_PORT_A_data_in, J1_q_a[2]_clock_0, , , );
J1_q_a[2]_PORT_B_data_in = H1_ram_rom_data_reg[2];
J1_q_a[2]_PORT_B_data_in_reg = DFFE(J1_q_a[2]_PORT_B_data_in, J1_q_a[2]_clock_1, , , );
J1_q_a[2]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[2]_PORT_A_address_reg = DFFE(J1_q_a[2]_PORT_A_address, J1_q_a[2]_clock_0, , , );
J1_q_a[2]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[2]_PORT_B_address_reg = DFFE(J1_q_a[2]_PORT_B_address, J1_q_a[2]_clock_1, , , );
J1_q_a[2]_PORT_A_write_enable = SW[17];
J1_q_a[2]_PORT_A_write_enable_reg = DFFE(J1_q_a[2]_PORT_A_write_enable, J1_q_a[2]_clock_0, , , );
J1_q_a[2]_PORT_B_write_enable = H1L3;
J1_q_a[2]_PORT_B_write_enable_reg = DFFE(J1_q_a[2]_PORT_B_write_enable, J1_q_a[2]_clock_1, , , );
J1_q_a[2]_clock_0 = CLOCK_50;
J1_q_a[2]_clock_1 = A1L110;
J1_q_a[2]_PORT_A_data_out = MEMORY(J1_q_a[2]_PORT_A_data_in_reg, J1_q_a[2]_PORT_B_data_in_reg, J1_q_a[2]_PORT_A_address_reg, J1_q_a[2]_PORT_B_address_reg, J1_q_a[2]_PORT_A_write_enable_reg, J1_q_a[2]_PORT_B_write_enable_reg, , , J1_q_a[2]_clock_0, J1_q_a[2]_clock_1, , , , );
J1_q_a[2] = J1_q_a[2]_PORT_A_data_out[0];

--J1_q_b[2] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[2]
J1_q_b[2]_PORT_A_data_in = SW[2];
J1_q_b[2]_PORT_A_data_in_reg = DFFE(J1_q_b[2]_PORT_A_data_in, J1_q_b[2]_clock_0, , , );
J1_q_b[2]_PORT_B_data_in = H1_ram_rom_data_reg[2];
J1_q_b[2]_PORT_B_data_in_reg = DFFE(J1_q_b[2]_PORT_B_data_in, J1_q_b[2]_clock_1, , , );
J1_q_b[2]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[2]_PORT_A_address_reg = DFFE(J1_q_b[2]_PORT_A_address, J1_q_b[2]_clock_0, , , );
J1_q_b[2]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[2]_PORT_B_address_reg = DFFE(J1_q_b[2]_PORT_B_address, J1_q_b[2]_clock_1, , , );
J1_q_b[2]_PORT_A_write_enable = SW[17];
J1_q_b[2]_PORT_A_write_enable_reg = DFFE(J1_q_b[2]_PORT_A_write_enable, J1_q_b[2]_clock_0, , , );
J1_q_b[2]_PORT_B_write_enable = H1L3;
J1_q_b[2]_PORT_B_write_enable_reg = DFFE(J1_q_b[2]_PORT_B_write_enable, J1_q_b[2]_clock_1, , , );
J1_q_b[2]_clock_0 = CLOCK_50;
J1_q_b[2]_clock_1 = A1L110;
J1_q_b[2]_PORT_B_data_out = MEMORY(J1_q_b[2]_PORT_A_data_in_reg, J1_q_b[2]_PORT_B_data_in_reg, J1_q_b[2]_PORT_A_address_reg, J1_q_b[2]_PORT_B_address_reg, J1_q_b[2]_PORT_A_write_enable_reg, J1_q_b[2]_PORT_B_write_enable_reg, , , J1_q_b[2]_clock_0, J1_q_b[2]_clock_1, , , , );
J1_q_b[2] = J1_q_b[2]_PORT_B_data_out[0];


--J1_q_a[3] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
J1_q_a[3]_PORT_A_data_in = SW[3];
J1_q_a[3]_PORT_A_data_in_reg = DFFE(J1_q_a[3]_PORT_A_data_in, J1_q_a[3]_clock_0, , , );
J1_q_a[3]_PORT_B_data_in = H1_ram_rom_data_reg[3];
J1_q_a[3]_PORT_B_data_in_reg = DFFE(J1_q_a[3]_PORT_B_data_in, J1_q_a[3]_clock_1, , , );
J1_q_a[3]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[3]_PORT_A_address_reg = DFFE(J1_q_a[3]_PORT_A_address, J1_q_a[3]_clock_0, , , );
J1_q_a[3]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[3]_PORT_B_address_reg = DFFE(J1_q_a[3]_PORT_B_address, J1_q_a[3]_clock_1, , , );
J1_q_a[3]_PORT_A_write_enable = SW[17];
J1_q_a[3]_PORT_A_write_enable_reg = DFFE(J1_q_a[3]_PORT_A_write_enable, J1_q_a[3]_clock_0, , , );
J1_q_a[3]_PORT_B_write_enable = H1L3;
J1_q_a[3]_PORT_B_write_enable_reg = DFFE(J1_q_a[3]_PORT_B_write_enable, J1_q_a[3]_clock_1, , , );
J1_q_a[3]_clock_0 = CLOCK_50;
J1_q_a[3]_clock_1 = A1L110;
J1_q_a[3]_PORT_A_data_out = MEMORY(J1_q_a[3]_PORT_A_data_in_reg, J1_q_a[3]_PORT_B_data_in_reg, J1_q_a[3]_PORT_A_address_reg, J1_q_a[3]_PORT_B_address_reg, J1_q_a[3]_PORT_A_write_enable_reg, J1_q_a[3]_PORT_B_write_enable_reg, , , J1_q_a[3]_clock_0, J1_q_a[3]_clock_1, , , , );
J1_q_a[3] = J1_q_a[3]_PORT_A_data_out[0];

--J1_q_b[3] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[3]
J1_q_b[3]_PORT_A_data_in = SW[3];
J1_q_b[3]_PORT_A_data_in_reg = DFFE(J1_q_b[3]_PORT_A_data_in, J1_q_b[3]_clock_0, , , );
J1_q_b[3]_PORT_B_data_in = H1_ram_rom_data_reg[3];
J1_q_b[3]_PORT_B_data_in_reg = DFFE(J1_q_b[3]_PORT_B_data_in, J1_q_b[3]_clock_1, , , );
J1_q_b[3]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[3]_PORT_A_address_reg = DFFE(J1_q_b[3]_PORT_A_address, J1_q_b[3]_clock_0, , , );
J1_q_b[3]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[3]_PORT_B_address_reg = DFFE(J1_q_b[3]_PORT_B_address, J1_q_b[3]_clock_1, , , );
J1_q_b[3]_PORT_A_write_enable = SW[17];
J1_q_b[3]_PORT_A_write_enable_reg = DFFE(J1_q_b[3]_PORT_A_write_enable, J1_q_b[3]_clock_0, , , );
J1_q_b[3]_PORT_B_write_enable = H1L3;
J1_q_b[3]_PORT_B_write_enable_reg = DFFE(J1_q_b[3]_PORT_B_write_enable, J1_q_b[3]_clock_1, , , );
J1_q_b[3]_clock_0 = CLOCK_50;
J1_q_b[3]_clock_1 = A1L110;
J1_q_b[3]_PORT_B_data_out = MEMORY(J1_q_b[3]_PORT_A_data_in_reg, J1_q_b[3]_PORT_B_data_in_reg, J1_q_b[3]_PORT_A_address_reg, J1_q_b[3]_PORT_B_address_reg, J1_q_b[3]_PORT_A_write_enable_reg, J1_q_b[3]_PORT_B_write_enable_reg, , , J1_q_b[3]_clock_0, J1_q_b[3]_clock_1, , , , );
J1_q_b[3] = J1_q_b[3]_PORT_B_data_out[0];


--D2L1 is SEG7_LUT:u2|oSEG[0]~70
D2L1 = J1_q_a[2] & !J1_q_a[1] & (J1_q_a[0] $ !J1_q_a[3]) # !J1_q_a[2] & J1_q_a[0] & (J1_q_a[1] $ !J1_q_a[3]);


--D2L2 is SEG7_LUT:u2|oSEG[1]~71
D2L2 = J1_q_a[1] & (J1_q_a[0] & (J1_q_a[3]) # !J1_q_a[0] & J1_q_a[2]) # !J1_q_a[1] & J1_q_a[2] & (J1_q_a[0] $ J1_q_a[3]);


--D2L3 is SEG7_LUT:u2|oSEG[2]~72
D2L3 = J1_q_a[2] & J1_q_a[3] & (J1_q_a[1] # !J1_q_a[0]) # !J1_q_a[2] & !J1_q_a[0] & J1_q_a[1] & !J1_q_a[3];


--D2L4 is SEG7_LUT:u2|oSEG[3]~73
D2L4 = J1_q_a[0] & (J1_q_a[1] $ !J1_q_a[2]) # !J1_q_a[0] & (J1_q_a[1] & !J1_q_a[2] & J1_q_a[3] # !J1_q_a[1] & J1_q_a[2] & !J1_q_a[3]);


--D2L5 is SEG7_LUT:u2|oSEG[4]~74
D2L5 = J1_q_a[1] & J1_q_a[0] & (!J1_q_a[3]) # !J1_q_a[1] & (J1_q_a[2] & (!J1_q_a[3]) # !J1_q_a[2] & J1_q_a[0]);


--D2L6 is SEG7_LUT:u2|oSEG[5]~75
D2L6 = J1_q_a[0] & (J1_q_a[3] $ (J1_q_a[1] # !J1_q_a[2])) # !J1_q_a[0] & J1_q_a[1] & !J1_q_a[2] & !J1_q_a[3];


--D2L7 is SEG7_LUT:u2|oSEG[6]~76
D2L7 = J1_q_a[0] & (J1_q_a[3] # J1_q_a[1] $ J1_q_a[2]) # !J1_q_a[0] & (J1_q_a[1] # J1_q_a[2] $ J1_q_a[3]);


--J1_q_a[4] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
J1_q_a[4]_PORT_A_data_in = SW[4];
J1_q_a[4]_PORT_A_data_in_reg = DFFE(J1_q_a[4]_PORT_A_data_in, J1_q_a[4]_clock_0, , , );
J1_q_a[4]_PORT_B_data_in = H1_ram_rom_data_reg[4];
J1_q_a[4]_PORT_B_data_in_reg = DFFE(J1_q_a[4]_PORT_B_data_in, J1_q_a[4]_clock_1, , , );
J1_q_a[4]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[4]_PORT_A_address_reg = DFFE(J1_q_a[4]_PORT_A_address, J1_q_a[4]_clock_0, , , );
J1_q_a[4]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[4]_PORT_B_address_reg = DFFE(J1_q_a[4]_PORT_B_address, J1_q_a[4]_clock_1, , , );
J1_q_a[4]_PORT_A_write_enable = SW[17];
J1_q_a[4]_PORT_A_write_enable_reg = DFFE(J1_q_a[4]_PORT_A_write_enable, J1_q_a[4]_clock_0, , , );
J1_q_a[4]_PORT_B_write_enable = H1L3;
J1_q_a[4]_PORT_B_write_enable_reg = DFFE(J1_q_a[4]_PORT_B_write_enable, J1_q_a[4]_clock_1, , , );
J1_q_a[4]_clock_0 = CLOCK_50;
J1_q_a[4]_clock_1 = A1L110;
J1_q_a[4]_PORT_A_data_out = MEMORY(J1_q_a[4]_PORT_A_data_in_reg, J1_q_a[4]_PORT_B_data_in_reg, J1_q_a[4]_PORT_A_address_reg, J1_q_a[4]_PORT_B_address_reg, J1_q_a[4]_PORT_A_write_enable_reg, J1_q_a[4]_PORT_B_write_enable_reg, , , J1_q_a[4]_clock_0, J1_q_a[4]_clock_1, , , , );
J1_q_a[4] = J1_q_a[4]_PORT_A_data_out[0];

--J1_q_b[4] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[4]
J1_q_b[4]_PORT_A_data_in = SW[4];
J1_q_b[4]_PORT_A_data_in_reg = DFFE(J1_q_b[4]_PORT_A_data_in, J1_q_b[4]_clock_0, , , );
J1_q_b[4]_PORT_B_data_in = H1_ram_rom_data_reg[4];
J1_q_b[4]_PORT_B_data_in_reg = DFFE(J1_q_b[4]_PORT_B_data_in, J1_q_b[4]_clock_1, , , );
J1_q_b[4]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[4]_PORT_A_address_reg = DFFE(J1_q_b[4]_PORT_A_address, J1_q_b[4]_clock_0, , , );
J1_q_b[4]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[4]_PORT_B_address_reg = DFFE(J1_q_b[4]_PORT_B_address, J1_q_b[4]_clock_1, , , );
J1_q_b[4]_PORT_A_write_enable = SW[17];
J1_q_b[4]_PORT_A_write_enable_reg = DFFE(J1_q_b[4]_PORT_A_write_enable, J1_q_b[4]_clock_0, , , );
J1_q_b[4]_PORT_B_write_enable = H1L3;
J1_q_b[4]_PORT_B_write_enable_reg = DFFE(J1_q_b[4]_PORT_B_write_enable, J1_q_b[4]_clock_1, , , );
J1_q_b[4]_clock_0 = CLOCK_50;
J1_q_b[4]_clock_1 = A1L110;
J1_q_b[4]_PORT_B_data_out = MEMORY(J1_q_b[4]_PORT_A_data_in_reg, J1_q_b[4]_PORT_B_data_in_reg, J1_q_b[4]_PORT_A_address_reg, J1_q_b[4]_PORT_B_address_reg, J1_q_b[4]_PORT_A_write_enable_reg, J1_q_b[4]_PORT_B_write_enable_reg, , , J1_q_b[4]_clock_0, J1_q_b[4]_clock_1, , , , );
J1_q_b[4] = J1_q_b[4]_PORT_B_data_out[0];


--J1_q_a[5] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
J1_q_a[5]_PORT_A_data_in = SW[5];
J1_q_a[5]_PORT_A_data_in_reg = DFFE(J1_q_a[5]_PORT_A_data_in, J1_q_a[5]_clock_0, , , );
J1_q_a[5]_PORT_B_data_in = H1_ram_rom_data_reg[5];
J1_q_a[5]_PORT_B_data_in_reg = DFFE(J1_q_a[5]_PORT_B_data_in, J1_q_a[5]_clock_1, , , );
J1_q_a[5]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[5]_PORT_A_address_reg = DFFE(J1_q_a[5]_PORT_A_address, J1_q_a[5]_clock_0, , , );
J1_q_a[5]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[5]_PORT_B_address_reg = DFFE(J1_q_a[5]_PORT_B_address, J1_q_a[5]_clock_1, , , );
J1_q_a[5]_PORT_A_write_enable = SW[17];
J1_q_a[5]_PORT_A_write_enable_reg = DFFE(J1_q_a[5]_PORT_A_write_enable, J1_q_a[5]_clock_0, , , );
J1_q_a[5]_PORT_B_write_enable = H1L3;
J1_q_a[5]_PORT_B_write_enable_reg = DFFE(J1_q_a[5]_PORT_B_write_enable, J1_q_a[5]_clock_1, , , );
J1_q_a[5]_clock_0 = CLOCK_50;
J1_q_a[5]_clock_1 = A1L110;
J1_q_a[5]_PORT_A_data_out = MEMORY(J1_q_a[5]_PORT_A_data_in_reg, J1_q_a[5]_PORT_B_data_in_reg, J1_q_a[5]_PORT_A_address_reg, J1_q_a[5]_PORT_B_address_reg, J1_q_a[5]_PORT_A_write_enable_reg, J1_q_a[5]_PORT_B_write_enable_reg, , , J1_q_a[5]_clock_0, J1_q_a[5]_clock_1, , , , );
J1_q_a[5] = J1_q_a[5]_PORT_A_data_out[0];

--J1_q_b[5] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[5]
J1_q_b[5]_PORT_A_data_in = SW[5];
J1_q_b[5]_PORT_A_data_in_reg = DFFE(J1_q_b[5]_PORT_A_data_in, J1_q_b[5]_clock_0, , , );
J1_q_b[5]_PORT_B_data_in = H1_ram_rom_data_reg[5];
J1_q_b[5]_PORT_B_data_in_reg = DFFE(J1_q_b[5]_PORT_B_data_in, J1_q_b[5]_clock_1, , , );
J1_q_b[5]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[5]_PORT_A_address_reg = DFFE(J1_q_b[5]_PORT_A_address, J1_q_b[5]_clock_0, , , );
J1_q_b[5]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[5]_PORT_B_address_reg = DFFE(J1_q_b[5]_PORT_B_address, J1_q_b[5]_clock_1, , , );
J1_q_b[5]_PORT_A_write_enable = SW[17];
J1_q_b[5]_PORT_A_write_enable_reg = DFFE(J1_q_b[5]_PORT_A_write_enable, J1_q_b[5]_clock_0, , , );
J1_q_b[5]_PORT_B_write_enable = H1L3;
J1_q_b[5]_PORT_B_write_enable_reg = DFFE(J1_q_b[5]_PORT_B_write_enable, J1_q_b[5]_clock_1, , , );
J1_q_b[5]_clock_0 = CLOCK_50;
J1_q_b[5]_clock_1 = A1L110;
J1_q_b[5]_PORT_B_data_out = MEMORY(J1_q_b[5]_PORT_A_data_in_reg, J1_q_b[5]_PORT_B_data_in_reg, J1_q_b[5]_PORT_A_address_reg, J1_q_b[5]_PORT_B_address_reg, J1_q_b[5]_PORT_A_write_enable_reg, J1_q_b[5]_PORT_B_write_enable_reg, , , J1_q_b[5]_clock_0, J1_q_b[5]_clock_1, , , , );
J1_q_b[5] = J1_q_b[5]_PORT_B_data_out[0];