part6.fit.eqn

基于FPGA的CPU设计 VHDL 编写

J1_q_b[0]_PORT_A_write_enable = SW[17];
J1_q_b[0]_PORT_A_write_enable_reg = DFFE(J1_q_b[0]_PORT_A_write_enable, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_write_enable = H1L3;
J1_q_b[0]_PORT_B_write_enable_reg = DFFE(J1_q_b[0]_PORT_B_write_enable, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_clock_0 = GLOBAL(A1L2);
J1_q_b[0]_clock_1 = GLOBAL(A1L112);
J1_q_b[0]_PORT_B_data_out = MEMORY(J1_q_b[0]_PORT_A_data_in_reg, J1_q_b[0]_PORT_B_data_in_reg, J1_q_b[0]_PORT_A_address_reg, J1_q_b[0]_PORT_B_address_reg, J1_q_b[0]_PORT_A_write_enable_reg, J1_q_b[0]_PORT_B_write_enable_reg, , , J1_q_b[0]_clock_0, J1_q_b[0]_clock_1, , , , );
J1_q_b[4] = J1_q_b[0]_PORT_B_data_out[4];

--J1_q_b[3] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[3] at M4K_X52_Y15
J1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_b[0]_PORT_A_data_in_reg = DFFE(J1_q_b[0]_PORT_A_data_in, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_b[0]_PORT_B_data_in_reg = DFFE(J1_q_b[0]_PORT_B_data_in, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[0]_PORT_A_address_reg = DFFE(J1_q_b[0]_PORT_A_address, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[0]_PORT_B_address_reg = DFFE(J1_q_b[0]_PORT_B_address, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_write_enable = SW[17];
J1_q_b[0]_PORT_A_write_enable_reg = DFFE(J1_q_b[0]_PORT_A_write_enable, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_write_enable = H1L3;
J1_q_b[0]_PORT_B_write_enable_reg = DFFE(J1_q_b[0]_PORT_B_write_enable, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_clock_0 = GLOBAL(A1L2);
J1_q_b[0]_clock_1 = GLOBAL(A1L112);
J1_q_b[0]_PORT_B_data_out = MEMORY(J1_q_b[0]_PORT_A_data_in_reg, J1_q_b[0]_PORT_B_data_in_reg, J1_q_b[0]_PORT_A_address_reg, J1_q_b[0]_PORT_B_address_reg, J1_q_b[0]_PORT_A_write_enable_reg, J1_q_b[0]_PORT_B_write_enable_reg, , , J1_q_b[0]_clock_0, J1_q_b[0]_clock_1, , , , );
J1_q_b[3] = J1_q_b[0]_PORT_B_data_out[3];

--J1_q_b[2] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[2] at M4K_X52_Y15
J1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_b[0]_PORT_A_data_in_reg = DFFE(J1_q_b[0]_PORT_A_data_in, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_b[0]_PORT_B_data_in_reg = DFFE(J1_q_b[0]_PORT_B_data_in, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[0]_PORT_A_address_reg = DFFE(J1_q_b[0]_PORT_A_address, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[0]_PORT_B_address_reg = DFFE(J1_q_b[0]_PORT_B_address, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_write_enable = SW[17];
J1_q_b[0]_PORT_A_write_enable_reg = DFFE(J1_q_b[0]_PORT_A_write_enable, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_write_enable = H1L3;
J1_q_b[0]_PORT_B_write_enable_reg = DFFE(J1_q_b[0]_PORT_B_write_enable, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_clock_0 = GLOBAL(A1L2);
J1_q_b[0]_clock_1 = GLOBAL(A1L112);
J1_q_b[0]_PORT_B_data_out = MEMORY(J1_q_b[0]_PORT_A_data_in_reg, J1_q_b[0]_PORT_B_data_in_reg, J1_q_b[0]_PORT_A_address_reg, J1_q_b[0]_PORT_B_address_reg, J1_q_b[0]_PORT_A_write_enable_reg, J1_q_b[0]_PORT_B_write_enable_reg, , , J1_q_b[0]_clock_0, J1_q_b[0]_clock_1, , , , );
J1_q_b[2] = J1_q_b[0]_PORT_B_data_out[2];

--J1_q_b[1] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[1] at M4K_X52_Y15
J1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_b[0]_PORT_A_data_in_reg = DFFE(J1_q_b[0]_PORT_A_data_in, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_b[0]_PORT_B_data_in_reg = DFFE(J1_q_b[0]_PORT_B_data_in, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[0]_PORT_A_address_reg = DFFE(J1_q_b[0]_PORT_A_address, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[0]_PORT_B_address_reg = DFFE(J1_q_b[0]_PORT_B_address, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_write_enable = SW[17];
J1_q_b[0]_PORT_A_write_enable_reg = DFFE(J1_q_b[0]_PORT_A_write_enable, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_write_enable = H1L3;
J1_q_b[0]_PORT_B_write_enable_reg = DFFE(J1_q_b[0]_PORT_B_write_enable, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_clock_0 = GLOBAL(A1L2);
J1_q_b[0]_clock_1 = GLOBAL(A1L112);
J1_q_b[0]_PORT_B_data_out = MEMORY(J1_q_b[0]_PORT_A_data_in_reg, J1_q_b[0]_PORT_B_data_in_reg, J1_q_b[0]_PORT_A_address_reg, J1_q_b[0]_PORT_B_address_reg, J1_q_b[0]_PORT_A_write_enable_reg, J1_q_b[0]_PORT_B_write_enable_reg, , , J1_q_b[0]_clock_0, J1_q_b[0]_clock_1, , , , );
J1_q_b[1] = J1_q_b[0]_PORT_B_data_out[1];


--D2L1 is SEG7_LUT:u2|oSEG[0]~70 at LCCOMB_X28_Y1_N26
D2L1 = J1_q_a[2] & !J1_q_a[1] & (J1_q_a[0] $ !J1_q_a[3]) # !J1_q_a[2] & J1_q_a[0] & (J1_q_a[1] $ !J1_q_a[3]);


--D2L2 is SEG7_LUT:u2|oSEG[1]~71 at LCCOMB_X28_Y1_N10
D2L2 = J1_q_a[1] & (J1_q_a[0] & (J1_q_a[3]) # !J1_q_a[0] & J1_q_a[2]) # !J1_q_a[1] & J1_q_a[2] & (J1_q_a[0] $ J1_q_a[3]);


--D2L3 is SEG7_LUT:u2|oSEG[2]~72 at LCCOMB_X28_Y1_N24
D2L3 = J1_q_a[2] & J1_q_a[3] & (J1_q_a[1] # !J1_q_a[0]) # !J1_q_a[2] & !J1_q_a[0] & J1_q_a[1] & !J1_q_a[3];


--D2L4 is SEG7_LUT:u2|oSEG[3]~73 at LCCOMB_X28_Y1_N8
D2L4 = J1_q_a[0] & (J1_q_a[2] $ !J1_q_a[1]) # !J1_q_a[0] & (J1_q_a[2] & !J1_q_a[1] & !J1_q_a[3] # !J1_q_a[2] & J1_q_a[1] & J1_q_a[3]);


--D2L5 is SEG7_LUT:u2|oSEG[4]~74 at LCCOMB_X28_Y1_N4
D2L5 = J1_q_a[1] & J1_q_a[0] & (!J1_q_a[3]) # !J1_q_a[1] & (J1_q_a[2] & (!J1_q_a[3]) # !J1_q_a[2] & J1_q_a[0]);


--D2L6 is SEG7_LUT:u2|oSEG[5]~75 at LCCOMB_X28_Y1_N12
D2L6 = J1_q_a[0] & (J1_q_a[3] $ (J1_q_a[1] # !J1_q_a[2])) # !J1_q_a[0] & !J1_q_a[2] & J1_q_a[1] & !J1_q_a[3];


--D2L7 is SEG7_LUT:u2|oSEG[6]~76 at LCCOMB_X28_Y1_N16
D2L7 = J1_q_a[0] & (J1_q_a[3] # J1_q_a[2] $ J1_q_a[1]) # !J1_q_a[0] & (J1_q_a[1] # J1_q_a[2] $ J1_q_a[3]);


--D1L1 is SEG7_LUT:u1|oSEG[0]~70 at LCCOMB_X64_Y5_N16
D1L1 = J1_q_a[7] & J1_q_a[4] & (J1_q_a[5] $ J1_q_a[6]) # !J1_q_a[7] & !J1_q_a[5] & (J1_q_a[4] $ J1_q_a[6]);


--D1L2 is SEG7_LUT:u1|oSEG[1]~71 at LCCOMB_X64_Y5_N22
D1L2 = J1_q_a[5] & (J1_q_a[4] & J1_q_a[7] # !J1_q_a[4] & (J1_q_a[6])) # !J1_q_a[5] & J1_q_a[6] & (J1_q_a[4] $ J1_q_a[7]);


--D1L3 is SEG7_LUT:u1|oSEG[2]~72 at LCCOMB_X64_Y5_N12
D1L3 = J1_q_a[7] & J1_q_a[6] & (J1_q_a[5] # !J1_q_a[4]) # !J1_q_a[7] & !J1_q_a[4] & J1_q_a[5] & !J1_q_a[6];


--D1L4 is SEG7_LUT:u1|oSEG[3]~73 at LCCOMB_X64_Y5_N8
D1L4 = J1_q_a[4] & (J1_q_a[5] $ (!J1_q_a[6])) # !J1_q_a[4] & (J1_q_a[5] & J1_q_a[7] & !J1_q_a[6] # !J1_q_a[5] & !J1_q_a[7] & J1_q_a[6]);


--D1L5 is SEG7_LUT:u1|oSEG[4]~74 at LCCOMB_X64_Y5_N4
D1L5 = J1_q_a[5] & J1_q_a[4] & !J1_q_a[7] # !J1_q_a[5] & (J1_q_a[6] & (!J1_q_a[7]) # !J1_q_a[6] & J1_q_a[4]);


--D1L6 is SEG7_LUT:u1|oSEG[5]~75 at LCCOMB_X64_Y5_N18
D1L6 = J1_q_a[4] & (J1_q_a[7] $ (J1_q_a[5] # !J1_q_a[6])) # !J1_q_a[4] & J1_q_a[5] & !J1_q_a[7] & !J1_q_a[6];


--D1L7 is SEG7_LUT:u1|oSEG[6]~76 at LCCOMB_X64_Y5_N6
D1L7 = J1_q_a[4] & (J1_q_a[7] # J1_q_a[5] $ J1_q_a[6]) # !J1_q_a[4] & (J1_q_a[5] # J1_q_a[7] $ J1_q_a[6]);


--read_addr[0] is read_addr[0] at LCFF_X60_Y7_N19
read_addr[0] = DFFEAS(A1L202, GLOBAL(A1L2), KEY[0],  , A1L87,  ,  ,  ,  );


--read_addr[1] is read_addr[1] at LCFF_X60_Y7_N21
read_addr[1] = DFFEAS(A1L205, GLOBAL(A1L2), KEY[0],  , A1L87,  ,  ,  ,  );


--read_addr[2] is read_addr[2] at LCFF_X60_Y7_N23
read_addr[2] = DFFEAS(A1L208, GLOBAL(A1L2), KEY[0],  , A1L87,  ,  ,  ,  );


--read_addr[3] is read_addr[3] at LCFF_X60_Y7_N25
read_addr[3] = DFFEAS(A1L211, GLOBAL(A1L2), KEY[0],  , A1L87,  ,  ,  ,  );


--D4L1 is SEG7_LUT:u4|oSEG[0]~70 at LCCOMB_X60_Y7_N16
D4L1 = read_addr[3] & read_addr[0] & (read_addr[1] $ read_addr[2]) # !read_addr[3] & !read_addr[1] & (read_addr[0] $ read_addr[2]);


--D4L2 is SEG7_LUT:u4|oSEG[1]~71 at LCCOMB_X60_Y7_N28
D4L2 = read_addr[1] & (read_addr[0] & read_addr[3] # !read_addr[0] & (read_addr[2])) # !read_addr[1] & read_addr[2] & (read_addr[0] $ read_addr[3]);


--D4L3 is SEG7_LUT:u4|oSEG[2]~72 at LCCOMB_X60_Y7_N10
D4L3 = read_addr[3] & read_addr[2] & (read_addr[1] # !read_addr[0]) # !read_addr[3] & read_addr[1] & !read_addr[0] & !read_addr[2];


--D4L4 is SEG7_LUT:u4|oSEG[3]~73 at LCCOMB_X60_Y7_N4
D4L4 = read_addr[0] & (read_addr[1] $ (!read_addr[2])) # !read_addr[0] & (read_addr[1] & read_addr[3] & !read_addr[2] # !read_addr[1] & !read_addr[3] & read_addr[2]);


--D4L5 is SEG7_LUT:u4|oSEG[4]~74 at LCCOMB_X60_Y7_N12
D4L5 = read_addr[1] & read_addr[0] & !read_addr[3] # !read_addr[1] & (read_addr[2] & (!read_addr[3]) # !read_addr[2] & read_addr[0]);


--D4L6 is SEG7_LUT:u4|oSEG[5]~75 at LCCOMB_X60_Y7_N8
D4L6 = read_addr[1] & !read_addr[3] & (read_addr[0] # !read_addr[2]) # !read_addr[1] & read_addr[0] & (read_addr[3] $ !read_addr[2]);


--D4L7 is SEG7_LUT:u4|oSEG[6]~76 at LCCOMB_X60_Y7_N2
D4L7 = read_addr[0] & (read_addr[3] # read_addr[1] $ read_addr[2]) # !read_addr[0] & (read_addr[1] # read_addr[3] $ read_addr[2]);


--read_addr[4] is read_addr[4] at LCFF_X60_Y7_N27
read_addr[4] = DFFEAS(A1L214, GLOBAL(A1L2), KEY[0],  , A1L87,  ,  ,  ,  );


--D6L1 is SEG7_LUT:u6|oSEG[0]~70 at LCCOMB_X1_Y14_N10
D6L1 = SW[3] & SW[0] & (SW[1] $ SW[2]) # !SW[3] & !SW[1] & (SW[0] $ SW[2]);


--D6L2 is SEG7_LUT:u6|oSEG[1]~71 at LCCOMB_X1_Y14_N26
D6L2 = SW[1] & (SW[0] & SW[3] # !SW[0] & (SW[2])) # !SW[1] & SW[2] & (SW[0] $ SW[3]);


--D6L3 is SEG7_LUT:u6|oSEG[2]~72 at LCCOMB_X1_Y14_N16
D6L3 = SW[3] & SW[2] & (SW[1] # !SW[0]) # !SW[3] & SW[1] & !SW[0] & !SW[2];


--D6L4 is SEG7_LUT:u6|oSEG[3]~73 at LCCOMB_X1_Y14_N12
D6L4 = SW[0] & (SW[1] $ (!SW[2])) # !SW[0] & (SW[1] & SW[3] & !SW[2] # !SW[1] & !SW[3] & SW[2]);


--D6L5 is SEG7_LUT:u6|oSEG[4]~74 at LCCOMB_X1_Y14_N28
D6L5 = SW[1] & SW[0] & !SW[3] # !SW[1] & (SW[2] & (!SW[3]) # !SW[2] & SW[0]);


--D6L6 is SEG7_LUT:u6|oSEG[5]~75 at LCCOMB_X1_Y14_N20
D6L6 = SW[1] & !SW[3] & (SW[0] # !SW[2]) # !SW[1] & SW[0] & (SW[3] $ !SW[2]);


--D6L7 is SEG7_LUT:u6|oSEG[6]~76 at LCCOMB_X1_Y14_N0
D6L7 = SW[0] & (SW[3] # SW[1] $ SW[2]) # !SW[0] & (SW[1] # SW[3] $ SW[2]);


--D5L1 is SEG7_LUT:u5|oSEG[0]~70 at LCCOMB_X1_Y15_N20
D5L1 = SW[7] & SW[4] & (SW[5] $ SW[6]) # !SW[7] & !SW[5] & (SW[4] $ SW[6]);


--D5L2 is SEG7_LUT:u5|oSEG[1]~71 at LCCOMB_X1_Y15_N12
D5L2 = SW[5] & (SW[4] & SW[7] # !SW[4] & (SW[6])) # !SW[5] & SW[6] & (SW[7] $ SW[4]);


--D5L3 is SEG7_LUT:u5|oSEG[2]~72 at LCCOMB_X1_Y15_N28
D5L3 = SW[7] & SW[6] & (SW[5] # !SW[4]) # !SW[7] & SW[5] & !SW[4] & !SW[6];


--D5L4 is SEG7_LUT:u5|oSEG[3]~73 at LCCOMB_X1_Y15_N0
D5L4 = SW[4] & (SW[5] $ (!SW[6])) # !SW[4] & (SW[5] & SW[7] & !SW[6] # !SW[5] & !SW[7] & SW[6]);


--D5L5 is SEG7_LUT:u5|oSEG[4]~74 at LCCOMB_X1_Y15_N4
D5L5 = SW[5] & !SW[7] & SW[4] # !SW[5] & (SW[6] & !SW[7] # !SW[6] & (SW[4]));


--D5L6 is SEG7_LUT:u5|oSEG[5]~75 at LCCOMB_X1_Y15_N26
D5L6 = SW[5] & !SW[7] & (SW[4] # !SW[6]) # !SW[5] & SW[4] & (SW[7] $ !SW[6]);


--D5L7 is SEG7_LUT:u5|oSEG[6]~76 at LCCOMB_X1_Y15_N10
D5L7 = SW[4] & (SW[7] # SW[5] $ SW[6]) # !SW[4] & (SW[5] # SW[7] $ SW[6]);


--D8L1 is SEG7_LUT:u8|oSEG[0]~70 at LCCOMB_X1_Y23_N4
D8L1 = SW[13] & !SW[12] & (SW[11] $ !SW[14]) # !SW[13] & SW[11] & (SW[12] $ !SW[14]);


--D8L2 is SEG7_LUT:u8|oSEG[1]~71 at LCCOMB_X1_Y23_N10
D8L2 = SW[12] & (SW[11] & (SW[14]) # !SW[11] & SW[13]) # !SW[12] & SW[13] & (SW[11] $ SW[14]);


--D8L3 is SEG7_LUT:u8|oSEG[2]~72 at LCCOMB_X1_Y23_N26
D8L3 = SW[13] & SW[14] & (SW[12] # !SW[11]) # !SW[13] & !SW[11] & SW[12] & !SW[14];


--D8L4 is SEG7_LUT:u8|oSEG[3]~73 at LCCOMB_X1_Y23_N18
D8L4 = SW[11] & (SW[13] $ !SW[12]) # !SW[11] & (SW[13] & !SW[12] & !SW[14] # !SW[13] & SW[12] & SW[14]);


--D8L5 is SEG7_LUT:u8|oSEG[4]~74 at LCCOMB_X1_Y23_N12
D8L5 = SW[12] & (SW[11] & !SW[14]) # !SW[12] & (SW[13] & (!SW[14]) # !SW[13] & SW[11]);