📄 part6.fit.eqn

📁 基于FPGA的CPU设计 VHDL 编写
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--J1_q_a[0] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[0] at M4K_X52_Y15
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 8, Port B Depth: 64, Port B Width: 8
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
J1_q_a[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_a[0]_PORT_A_data_in_reg = DFFE(J1_q_a[0]_PORT_A_data_in, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_a[0]_PORT_B_data_in_reg = DFFE(J1_q_a[0]_PORT_B_data_in, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[0]_PORT_B_address_reg = DFFE(J1_q_a[0]_PORT_B_address, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_write_enable = SW[17];
J1_q_a[0]_PORT_A_write_enable_reg = DFFE(J1_q_a[0]_PORT_A_write_enable, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_write_enable = H1L3;
J1_q_a[0]_PORT_B_write_enable_reg = DFFE(J1_q_a[0]_PORT_B_write_enable, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_clock_0 = GLOBAL(A1L2);
J1_q_a[0]_clock_1 = GLOBAL(A1L112);
J1_q_a[0]_PORT_A_data_out = MEMORY(J1_q_a[0]_PORT_A_data_in_reg, J1_q_a[0]_PORT_B_data_in_reg, J1_q_a[0]_PORT_A_address_reg, J1_q_a[0]_PORT_B_address_reg, J1_q_a[0]_PORT_A_write_enable_reg, J1_q_a[0]_PORT_B_write_enable_reg, , , J1_q_a[0]_clock_0, J1_q_a[0]_clock_1, , , , );
J1_q_a[0] = J1_q_a[0]_PORT_A_data_out[0];

--J1_q_b[0] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[0] at M4K_X52_Y15
J1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_b[0]_PORT_A_data_in_reg = DFFE(J1_q_b[0]_PORT_A_data_in, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_b[0]_PORT_B_data_in_reg = DFFE(J1_q_b[0]_PORT_B_data_in, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[0]_PORT_A_address_reg = DFFE(J1_q_b[0]_PORT_A_address, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[0]_PORT_B_address_reg = DFFE(J1_q_b[0]_PORT_B_address, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_write_enable = SW[17];
J1_q_b[0]_PORT_A_write_enable_reg = DFFE(J1_q_b[0]_PORT_A_write_enable, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_write_enable = H1L3;
J1_q_b[0]_PORT_B_write_enable_reg = DFFE(J1_q_b[0]_PORT_B_write_enable, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_clock_0 = GLOBAL(A1L2);
J1_q_b[0]_clock_1 = GLOBAL(A1L112);
J1_q_b[0]_PORT_B_data_out = MEMORY(J1_q_b[0]_PORT_A_data_in_reg, J1_q_b[0]_PORT_B_data_in_reg, J1_q_b[0]_PORT_A_address_reg, J1_q_b[0]_PORT_B_address_reg, J1_q_b[0]_PORT_A_write_enable_reg, J1_q_b[0]_PORT_B_write_enable_reg, , , J1_q_b[0]_clock_0, J1_q_b[0]_clock_1, , , , );
J1_q_b[0] = J1_q_b[0]_PORT_B_data_out[0];

--J1_q_a[7] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[7] at M4K_X52_Y15
J1_q_a[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_a[0]_PORT_A_data_in_reg = DFFE(J1_q_a[0]_PORT_A_data_in, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_a[0]_PORT_B_data_in_reg = DFFE(J1_q_a[0]_PORT_B_data_in, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[0]_PORT_B_address_reg = DFFE(J1_q_a[0]_PORT_B_address, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_write_enable = SW[17];
J1_q_a[0]_PORT_A_write_enable_reg = DFFE(J1_q_a[0]_PORT_A_write_enable, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_write_enable = H1L3;
J1_q_a[0]_PORT_B_write_enable_reg = DFFE(J1_q_a[0]_PORT_B_write_enable, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_clock_0 = GLOBAL(A1L2);
J1_q_a[0]_clock_1 = GLOBAL(A1L112);
J1_q_a[0]_PORT_A_data_out = MEMORY(J1_q_a[0]_PORT_A_data_in_reg, J1_q_a[0]_PORT_B_data_in_reg, J1_q_a[0]_PORT_A_address_reg, J1_q_a[0]_PORT_B_address_reg, J1_q_a[0]_PORT_A_write_enable_reg, J1_q_a[0]_PORT_B_write_enable_reg, , , J1_q_a[0]_clock_0, J1_q_a[0]_clock_1, , , , );
J1_q_a[7] = J1_q_a[0]_PORT_A_data_out[7];

--J1_q_a[6] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[6] at M4K_X52_Y15
J1_q_a[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_a[0]_PORT_A_data_in_reg = DFFE(J1_q_a[0]_PORT_A_data_in, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_a[0]_PORT_B_data_in_reg = DFFE(J1_q_a[0]_PORT_B_data_in, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[0]_PORT_B_address_reg = DFFE(J1_q_a[0]_PORT_B_address, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_write_enable = SW[17];
J1_q_a[0]_PORT_A_write_enable_reg = DFFE(J1_q_a[0]_PORT_A_write_enable, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_write_enable = H1L3;
J1_q_a[0]_PORT_B_write_enable_reg = DFFE(J1_q_a[0]_PORT_B_write_enable, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_clock_0 = GLOBAL(A1L2);
J1_q_a[0]_clock_1 = GLOBAL(A1L112);
J1_q_a[0]_PORT_A_data_out = MEMORY(J1_q_a[0]_PORT_A_data_in_reg, J1_q_a[0]_PORT_B_data_in_reg, J1_q_a[0]_PORT_A_address_reg, J1_q_a[0]_PORT_B_address_reg, J1_q_a[0]_PORT_A_write_enable_reg, J1_q_a[0]_PORT_B_write_enable_reg, , , J1_q_a[0]_clock_0, J1_q_a[0]_clock_1, , , , );
J1_q_a[6] = J1_q_a[0]_PORT_A_data_out[6];

--J1_q_a[5] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[5] at M4K_X52_Y15
J1_q_a[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_a[0]_PORT_A_data_in_reg = DFFE(J1_q_a[0]_PORT_A_data_in, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_a[0]_PORT_B_data_in_reg = DFFE(J1_q_a[0]_PORT_B_data_in, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[0]_PORT_B_address_reg = DFFE(J1_q_a[0]_PORT_B_address, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_write_enable = SW[17];
J1_q_a[0]_PORT_A_write_enable_reg = DFFE(J1_q_a[0]_PORT_A_write_enable, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_write_enable = H1L3;
J1_q_a[0]_PORT_B_write_enable_reg = DFFE(J1_q_a[0]_PORT_B_write_enable, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_clock_0 = GLOBAL(A1L2);
J1_q_a[0]_clock_1 = GLOBAL(A1L112);
J1_q_a[0]_PORT_A_data_out = MEMORY(J1_q_a[0]_PORT_A_data_in_reg, J1_q_a[0]_PORT_B_data_in_reg, J1_q_a[0]_PORT_A_address_reg, J1_q_a[0]_PORT_B_address_reg, J1_q_a[0]_PORT_A_write_enable_reg, J1_q_a[0]_PORT_B_write_enable_reg, , , J1_q_a[0]_clock_0, J1_q_a[0]_clock_1, , , , );
J1_q_a[5] = J1_q_a[0]_PORT_A_data_out[5];

--J1_q_a[4] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[4] at M4K_X52_Y15
J1_q_a[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_a[0]_PORT_A_data_in_reg = DFFE(J1_q_a[0]_PORT_A_data_in, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_a[0]_PORT_B_data_in_reg = DFFE(J1_q_a[0]_PORT_B_data_in, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[0]_PORT_B_address_reg = DFFE(J1_q_a[0]_PORT_B_address, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_write_enable = SW[17];
J1_q_a[0]_PORT_A_write_enable_reg = DFFE(J1_q_a[0]_PORT_A_write_enable, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_write_enable = H1L3;
J1_q_a[0]_PORT_B_write_enable_reg = DFFE(J1_q_a[0]_PORT_B_write_enable, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_clock_0 = GLOBAL(A1L2);
J1_q_a[0]_clock_1 = GLOBAL(A1L112);
J1_q_a[0]_PORT_A_data_out = MEMORY(J1_q_a[0]_PORT_A_data_in_reg, J1_q_a[0]_PORT_B_data_in_reg, J1_q_a[0]_PORT_A_address_reg, J1_q_a[0]_PORT_B_address_reg, J1_q_a[0]_PORT_A_write_enable_reg, J1_q_a[0]_PORT_B_write_enable_reg, , , J1_q_a[0]_clock_0, J1_q_a[0]_clock_1, , , , );
J1_q_a[4] = J1_q_a[0]_PORT_A_data_out[4];

--J1_q_a[3] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[3] at M4K_X52_Y15
J1_q_a[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_a[0]_PORT_A_data_in_reg = DFFE(J1_q_a[0]_PORT_A_data_in, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_a[0]_PORT_B_data_in_reg = DFFE(J1_q_a[0]_PORT_B_data_in, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[0]_PORT_B_address_reg = DFFE(J1_q_a[0]_PORT_B_address, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_write_enable = SW[17];
J1_q_a[0]_PORT_A_write_enable_reg = DFFE(J1_q_a[0]_PORT_A_write_enable, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_write_enable = H1L3;
J1_q_a[0]_PORT_B_write_enable_reg = DFFE(J1_q_a[0]_PORT_B_write_enable, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_clock_0 = GLOBAL(A1L2);
J1_q_a[0]_clock_1 = GLOBAL(A1L112);
J1_q_a[0]_PORT_A_data_out = MEMORY(J1_q_a[0]_PORT_A_data_in_reg, J1_q_a[0]_PORT_B_data_in_reg, J1_q_a[0]_PORT_A_address_reg, J1_q_a[0]_PORT_B_address_reg, J1_q_a[0]_PORT_A_write_enable_reg, J1_q_a[0]_PORT_B_write_enable_reg, , , J1_q_a[0]_clock_0, J1_q_a[0]_clock_1, , , , );
J1_q_a[3] = J1_q_a[0]_PORT_A_data_out[3];

--J1_q_a[2] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[2] at M4K_X52_Y15
J1_q_a[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_a[0]_PORT_A_data_in_reg = DFFE(J1_q_a[0]_PORT_A_data_in, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_a[0]_PORT_B_data_in_reg = DFFE(J1_q_a[0]_PORT_B_data_in, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[0]_PORT_B_address_reg = DFFE(J1_q_a[0]_PORT_B_address, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_write_enable = SW[17];
J1_q_a[0]_PORT_A_write_enable_reg = DFFE(J1_q_a[0]_PORT_A_write_enable, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_write_enable = H1L3;
J1_q_a[0]_PORT_B_write_enable_reg = DFFE(J1_q_a[0]_PORT_B_write_enable, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_clock_0 = GLOBAL(A1L2);
J1_q_a[0]_clock_1 = GLOBAL(A1L112);
J1_q_a[0]_PORT_A_data_out = MEMORY(J1_q_a[0]_PORT_A_data_in_reg, J1_q_a[0]_PORT_B_data_in_reg, J1_q_a[0]_PORT_A_address_reg, J1_q_a[0]_PORT_B_address_reg, J1_q_a[0]_PORT_A_write_enable_reg, J1_q_a[0]_PORT_B_write_enable_reg, , , J1_q_a[0]_clock_0, J1_q_a[0]_clock_1, , , , );
J1_q_a[2] = J1_q_a[0]_PORT_A_data_out[2];

--J1_q_a[1] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[1] at M4K_X52_Y15
J1_q_a[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_a[0]_PORT_A_data_in_reg = DFFE(J1_q_a[0]_PORT_A_data_in, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_a[0]_PORT_B_data_in_reg = DFFE(J1_q_a[0]_PORT_B_data_in, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_a[0]_PORT_B_address_reg = DFFE(J1_q_a[0]_PORT_B_address, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_PORT_A_write_enable = SW[17];
J1_q_a[0]_PORT_A_write_enable_reg = DFFE(J1_q_a[0]_PORT_A_write_enable, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_PORT_B_write_enable = H1L3;
J1_q_a[0]_PORT_B_write_enable_reg = DFFE(J1_q_a[0]_PORT_B_write_enable, J1_q_a[0]_clock_1, , , );
J1_q_a[0]_clock_0 = GLOBAL(A1L2);
J1_q_a[0]_clock_1 = GLOBAL(A1L112);
J1_q_a[0]_PORT_A_data_out = MEMORY(J1_q_a[0]_PORT_A_data_in_reg, J1_q_a[0]_PORT_B_data_in_reg, J1_q_a[0]_PORT_A_address_reg, J1_q_a[0]_PORT_B_address_reg, J1_q_a[0]_PORT_A_write_enable_reg, J1_q_a[0]_PORT_B_write_enable_reg, , , J1_q_a[0]_clock_0, J1_q_a[0]_clock_1, , , , );
J1_q_a[1] = J1_q_a[0]_PORT_A_data_out[1];

--J1_q_b[7] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[7] at M4K_X52_Y15
J1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_b[0]_PORT_A_data_in_reg = DFFE(J1_q_b[0]_PORT_A_data_in, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_b[0]_PORT_B_data_in_reg = DFFE(J1_q_b[0]_PORT_B_data_in, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[0]_PORT_A_address_reg = DFFE(J1_q_b[0]_PORT_A_address, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[0]_PORT_B_address_reg = DFFE(J1_q_b[0]_PORT_B_address, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_write_enable = SW[17];
J1_q_b[0]_PORT_A_write_enable_reg = DFFE(J1_q_b[0]_PORT_A_write_enable, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_write_enable = H1L3;
J1_q_b[0]_PORT_B_write_enable_reg = DFFE(J1_q_b[0]_PORT_B_write_enable, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_clock_0 = GLOBAL(A1L2);
J1_q_b[0]_clock_1 = GLOBAL(A1L112);
J1_q_b[0]_PORT_B_data_out = MEMORY(J1_q_b[0]_PORT_A_data_in_reg, J1_q_b[0]_PORT_B_data_in_reg, J1_q_b[0]_PORT_A_address_reg, J1_q_b[0]_PORT_B_address_reg, J1_q_b[0]_PORT_A_write_enable_reg, J1_q_b[0]_PORT_B_write_enable_reg, , , J1_q_b[0]_clock_0, J1_q_b[0]_clock_1, , , , );
J1_q_b[7] = J1_q_b[0]_PORT_B_data_out[7];

--J1_q_b[6] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[6] at M4K_X52_Y15
J1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_b[0]_PORT_A_data_in_reg = DFFE(J1_q_b[0]_PORT_A_data_in, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_b[0]_PORT_B_data_in_reg = DFFE(J1_q_b[0]_PORT_B_data_in, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[0]_PORT_A_address_reg = DFFE(J1_q_b[0]_PORT_A_address, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[0]_PORT_B_address_reg = DFFE(J1_q_b[0]_PORT_B_address, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_write_enable = SW[17];
J1_q_b[0]_PORT_A_write_enable_reg = DFFE(J1_q_b[0]_PORT_A_write_enable, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_write_enable = H1L3;
J1_q_b[0]_PORT_B_write_enable_reg = DFFE(J1_q_b[0]_PORT_B_write_enable, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_clock_0 = GLOBAL(A1L2);
J1_q_b[0]_clock_1 = GLOBAL(A1L112);
J1_q_b[0]_PORT_B_data_out = MEMORY(J1_q_b[0]_PORT_A_data_in_reg, J1_q_b[0]_PORT_B_data_in_reg, J1_q_b[0]_PORT_A_address_reg, J1_q_b[0]_PORT_B_address_reg, J1_q_b[0]_PORT_A_write_enable_reg, J1_q_b[0]_PORT_B_write_enable_reg, , , J1_q_b[0]_clock_0, J1_q_b[0]_clock_1, , , , );
J1_q_b[6] = J1_q_b[0]_PORT_B_data_out[6];

--J1_q_b[5] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[5] at M4K_X52_Y15
J1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_b[0]_PORT_A_data_in_reg = DFFE(J1_q_b[0]_PORT_A_data_in, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_b[0]_PORT_B_data_in_reg = DFFE(J1_q_b[0]_PORT_B_data_in, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[0]_PORT_A_address_reg = DFFE(J1_q_b[0]_PORT_A_address, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[0]_PORT_B_address_reg = DFFE(J1_q_b[0]_PORT_B_address, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_write_enable = SW[17];
J1_q_b[0]_PORT_A_write_enable_reg = DFFE(J1_q_b[0]_PORT_A_write_enable, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_write_enable = H1L3;
J1_q_b[0]_PORT_B_write_enable_reg = DFFE(J1_q_b[0]_PORT_B_write_enable, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_clock_0 = GLOBAL(A1L2);
J1_q_b[0]_clock_1 = GLOBAL(A1L112);
J1_q_b[0]_PORT_B_data_out = MEMORY(J1_q_b[0]_PORT_A_data_in_reg, J1_q_b[0]_PORT_B_data_in_reg, J1_q_b[0]_PORT_A_address_reg, J1_q_b[0]_PORT_B_address_reg, J1_q_b[0]_PORT_A_write_enable_reg, J1_q_b[0]_PORT_B_write_enable_reg, , , J1_q_b[0]_clock_0, J1_q_b[0]_clock_1, , , , );
J1_q_b[5] = J1_q_b[0]_PORT_B_data_out[5];

--J1_q_b[4] is ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_b[4] at M4K_X52_Y15
J1_q_b[0]_PORT_A_data_in = BUS(SW[0], SW[1], SW[2], SW[3], SW[4], SW[5], SW[6], SW[7]);
J1_q_b[0]_PORT_A_data_in_reg = DFFE(J1_q_b[0]_PORT_A_data_in, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_data_in = BUS(H1_ram_rom_data_reg[0], H1_ram_rom_data_reg[1], H1_ram_rom_data_reg[2], H1_ram_rom_data_reg[3], H1_ram_rom_data_reg[4], H1_ram_rom_data_reg[5], H1_ram_rom_data_reg[6], H1_ram_rom_data_reg[7]);
J1_q_b[0]_PORT_B_data_in_reg = DFFE(J1_q_b[0]_PORT_B_data_in, J1_q_b[0]_clock_1, , , );
J1_q_b[0]_PORT_A_address = BUS(~GND, read_addr[0], read_addr[1], read_addr[2], read_addr[3], read_addr[4]);
J1_q_b[0]_PORT_A_address_reg = DFFE(J1_q_b[0]_PORT_A_address, J1_q_b[0]_clock_0, , , );
J1_q_b[0]_PORT_B_address = BUS(~GND, H1_ram_rom_addr_reg[0], H1_ram_rom_addr_reg[1], H1_ram_rom_addr_reg[2], H1_ram_rom_addr_reg[3], H1_ram_rom_addr_reg[4]);
J1_q_b[0]_PORT_B_address_reg = DFFE(J1_q_b[0]_PORT_B_address, J1_q_b[0]_clock_1, , , );
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