part6.tan.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "ITDB_FULL_TPD_RESULT" "SW\[13\] HEX6\[0\] 10.623 ns Longest " "Info: Longest tpd from source pin \"SW\[13\]\" to destination pin \"HEX6\[0\]\" is 10.623 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.822 ns) 0.822 ns SW\[13\] 1 PIN PIN_T7 7 " "Info: 1: + IC(0.000 ns) + CELL(0.822 ns) = 0.822 ns; Loc. = PIN_T7; Fanout = 7; PIN Node = 'SW\[13\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "" { SW[13] } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.668 ns) + CELL(0.438 ns) 6.928 ns SEG7_LUT:u8\|oSEG\[0\]~70 2 COMB LCCOMB_X1_Y23_N4 1 " "Info: 2: + IC(5.668 ns) + CELL(0.438 ns) = 6.928 ns; Loc. = LCCOMB_X1_Y23_N4; Fanout = 1; COMB Node = 'SEG7_LUT:u8\|oSEG\[0\]~70'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "6.106 ns" { SW[13] SEG7_LUT:u8|oSEG[0]~70 } "NODE_NAME" } "" } } { "SEG7_LUT.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/SEG7_LUT.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.063 ns) + CELL(2.632 ns) 10.623 ns HEX6\[0\] 3 PIN PIN_R2 0 " "Info: 3: + IC(1.063 ns) + CELL(2.632 ns) = 10.623 ns; Loc. = PIN_R2; Fanout = 0; PIN Node = 'HEX6\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "3.695 ns" { SEG7_LUT:u8|oSEG[0]~70 HEX6[0] } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.892 ns ( 36.64 % ) " "Info: Total cell delay = 3.892 ns ( 36.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.731 ns ( 63.36 % ) " "Info: Total interconnect delay = 6.731 ns ( 63.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "10.623 ns" { SW[13] SEG7_LUT:u8|oSEG[0]~70 HEX6[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.623 ns" { SW[13] SW[13]~combout SEG7_LUT:u8|oSEG[0]~70 HEX6[0] } { 0.000ns 0.000ns 5.668ns 1.063ns } { 0.000ns 0.822ns 0.438ns 2.632ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\] altera_internal_jtag altera_internal_jtag~TCKUTAP 1.184 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.184 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 3.824 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 3.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.273 ns) + CELL(0.000 ns) 2.273 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G11 125 " "Info: 2: + IC(2.273 ns) + CELL(0.000 ns) = 2.273 ns; Loc. = CLKCTRL_G11; Fanout = 125; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c