part6.tan.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "ITDB_TSU_RESULT" "ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|ram_block4a0~porta_we_reg SW\[17\] CLOCK_50 4.489 ns memory " "Info: tsu for memory \"ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|ram_block4a0~porta_we_reg\" (data pin = \"SW\[17\]\", clock pin = \"CLOCK_50\") is 4.489 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.178 ns + Longest pin memory " "Info: + Longest pin to memory delay is 7.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns SW\[17\] 1 PIN PIN_V2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 2; PIN Node = 'SW\[17\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "" { SW[17] } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.017 ns) + CELL(0.309 ns) 7.178 ns ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|ram_block4a0~porta_we_reg 2 MEM M4K_X52_Y15 8 " "Info: 2: + IC(6.017 ns) + CELL(0.309 ns) = 7.178 ns; Loc. = M4K_X52_Y15; Fanout = 8; MEM Node = 'ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|ram_block4a0~porta_we_reg'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "6.326 ns" { SW[17] ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } "NODE_NAME" } "" } } { "db/altsyncram_pq12.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_pq12.tdf" 50 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.161 ns ( 16.17 % ) " "Info: Total cell delay = 1.161 ns ( 16.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.017 ns ( 83.83 % ) " "Info: Total interconnect delay = 6.017 ns ( 83.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "7.178 ns" { SW[17] ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.178 ns" { SW[17] SW[17]~combout ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } { 0.000ns 0.000ns 6.017ns } { 0.000ns 0.852ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_pq12.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_pq12.tdf" 50 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.724 ns - Shortest memory " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination memory is 2.724 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "" { CLOCK_50 } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.956 ns) + CELL(0.661 ns) 2.724 ns ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|ram_block4a0~porta_we_reg 3 MEM M4K_X52_Y15 8 " "Info: 3: + IC(0.956 ns) + CELL(0.661 ns) = 2.724 ns; Loc. = M4K_X52_Y15; Fanout = 8; MEM Node = 'ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|ram_block4a0~porta_we_reg'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "1.617 ns" { CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } "NODE_NAME" } "" } } { "db/altsyncram_pq12.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_pq12.tdf" 50 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 60.57 % ) " "Info: Total cell delay = 1.650 ns ( 60.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.074 ns ( 39.43 % ) " "Info: Total interconnect delay = 1.074 ns ( 39.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.724 ns" { CLOCK_50 CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.724 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } { 0.000ns 0.000ns 0.118ns 0.956ns } { 0.000ns 0.989ns 0.000ns 0.661ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "7.178 ns" { SW[17] ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.178 ns" { SW[17] SW[17]~combout ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } { 0.000ns 0.000ns 6.017ns } { 0.000ns 0.852ns 0.309ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.724 ns" { CLOCK_50 CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.724 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } { 0.000ns 0.000ns 0.118ns 0.956ns } { 0.000ns 0.989ns 0.000ns 0.661ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 HEX0\[0\] ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|ram_block4a0~porta_we_reg 13.501 ns memory " "Info: tco from clock \"CLOCK_50\" to destination pin \"HEX0\[0\]\" through memory \"ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|ram_block4a0~porta_we_reg\" is 13.501 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.724 ns + Longest memory " "Info: + Longest clock path from clock \"CLOCK_50\" to source memory is 2.724 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "" { CLOCK_50 } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.956 ns) + CELL(0.661 ns) 2.724 ns ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|ram_block4a0~porta_we_reg 3 MEM M4K_X52_Y15 8 " "Info: 3: + IC(0.956 ns) + CELL(0.661 ns) = 2.724 ns; Loc. = M4K_X52_Y15; Fanout = 8; MEM Node = 'ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|ram_block4a0~porta_we_reg'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "1.617 ns" { CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } "NODE_NAME" } "" } } { "db/altsyncram_pq12.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_pq12.tdf" 50 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 60.57 % ) " "Info: Total cell delay = 1.650 ns ( 60.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.074 ns ( 39.43 % ) " "Info: Total interconnect delay = 1.074 ns ( 39.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.724 ns" { CLOCK_50 CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.724 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } { 0.000ns 0.000ns 0.118ns 0.956ns } { 0.000ns 0.989ns 0.000ns 0.661ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "db/altsyncram_pq12.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_pq12.tdf" 50 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.568 ns + Longest memory pin " "Info: + Longest memory to pin delay is 10.568 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|ram_block4a0~porta_we_reg 1 MEM M4K_X52_Y15 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X52_Y15; Fanout = 8; MEM Node = 'ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|ram_block4a0~porta_we_reg'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } "NODE_NAME" } "" } } { "db/altsyncram_pq12.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_pq12.tdf" 50 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.993 ns) 2.993 ns ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|q_a\[2\] 2 MEM M4K_X52_Y15 7 " "Info: 2: + IC(0.000 ns) + CELL(2.993 ns) = 2.993 ns; Loc. = M4K_X52_Y15; Fanout = 7; MEM Node = 'ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\|q_a\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.993 ns" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[2] } "NODE_NAME" } "" } } { "db/altsyncram_pq12.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_pq12.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.551 ns) + CELL(0.416 ns) 6.960 ns SEG7_LUT:u2\|oSEG\[0\]~70 3 COMB LCCOMB_X28_Y1_N26 1 " "Info: 3: + IC(3.551 ns) + CELL(0.416 ns) = 6.960 ns; Loc. = LCCOMB_X28_Y1_N26; Fanout = 1; COMB Node = 'SEG7_LUT:u2\|oSEG\[0\]~70'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "3.967 ns" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[2] SEG7_LUT:u2|oSEG[0]~70 } "NODE_NAME" } "" } } { "SEG7_LUT.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/SEG7_LUT.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(2.788 ns) 10.568 ns HEX0\[0\] 4 PIN PIN_AF10 0 " "Info: 4: + IC(0.820 ns) + CELL(2.788 ns) = 10.568 ns; Loc. = PIN_AF10; Fanout = 0; PIN Node = 'HEX0\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "3.608 ns" { SEG7_LUT:u2|oSEG[0]~70 HEX0[0] } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.197 ns ( 58.64 % ) " "Info: Total cell delay = 6.197 ns ( 58.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.371 ns ( 41.36 % ) " "Info: Total interconnect delay = 4.371 ns ( 41.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "10.568 ns" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[2] SEG7_LUT:u2|oSEG[0]~70 HEX0[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.568 ns" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[2] SEG7_LUT:u2|oSEG[0]~70 HEX0[0] } { 0.000ns 0.000ns 3.551ns 0.820ns } { 0.000ns 2.993ns 0.416ns 2.788ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.724 ns" { CLOCK_50 CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.724 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg } { 0.000ns 0.000ns 0.118ns 0.956ns } { 0.000ns 0.989ns 0.000ns 0.661ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "10.568 ns" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[2] SEG7_LUT:u2|oSEG[0]~70 HEX0[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.568 ns" { ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|q_a[2] SEG7_LUT:u2|oSEG[0]~70 HEX0[0] } { 0.000ns 0.000ns 3.551ns 0.820ns } { 0.000ns 2.993ns 0.416ns 2.788ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}