part6.tan.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register count\[14\] register read_addr\[4\] 146.48 MHz 6.827 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 146.48 MHz between source register \"count\[14\]\" and destination register \"read_addr\[4\]\" (period= 6.827 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.633 ns + Longest register register " "Info: + Longest register to register delay is 6.633 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[14\] 1 REG LCFF_X31_Y27_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y27_N3; Fanout = 3; REG Node = 'count\[14\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "" { count[14] } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.789 ns) + CELL(0.438 ns) 1.227 ns LessThan~399 2 COMB LCCOMB_X31_Y28_N4 1 " "Info: 2: + IC(0.789 ns) + CELL(0.438 ns) = 1.227 ns; Loc. = LCCOMB_X31_Y28_N4; Fanout = 1; COMB Node = 'LessThan~399'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "1.227 ns" { count[14] LessThan~399 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.275 ns) 2.224 ns LessThan~401 3 COMB LCCOMB_X31_Y27_N30 1 " "Info: 3: + IC(0.722 ns) + CELL(0.275 ns) = 2.224 ns; Loc. = LCCOMB_X31_Y27_N30; Fanout = 1; COMB Node = 'LessThan~401'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "0.997 ns" { LessThan~399 LessThan~401 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.252 ns) + CELL(0.378 ns) 2.854 ns LessThan~404 4 COMB LCCOMB_X31_Y27_N28 31 " "Info: 4: + IC(0.252 ns) + CELL(0.378 ns) = 2.854 ns; Loc. = LCCOMB_X31_Y27_N28; Fanout = 31; COMB Node = 'LessThan~404'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "0.630 ns" { LessThan~401 LessThan~404 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.119 ns) + CELL(0.660 ns) 6.633 ns read_addr\[4\] 5 REG LCFF_X60_Y7_N27 6 " "Info: 5: + IC(3.119 ns) + CELL(0.660 ns) = 6.633 ns; Loc. = LCFF_X60_Y7_N27; Fanout = 6; REG Node = 'read_addr\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "3.779 ns" { LessThan~404 read_addr[4] } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.751 ns ( 26.40 % ) " "Info: Total cell delay = 1.751 ns ( 26.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.882 ns ( 73.60 % ) " "Info: Total interconnect delay = 4.882 ns ( 73.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "6.633 ns" { count[14] LessThan~399 LessThan~401 LessThan~404 read_addr[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.633 ns" { count[14] LessThan~399 LessThan~401 LessThan~404 read_addr[4] } { 0.000ns 0.789ns 0.722ns 0.252ns 3.119ns } { 0.000ns 0.438ns 0.275ns 0.378ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.020 ns - Smallest " "Info: - Smallest clock skew is 0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.668 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "" { CLOCK_50 } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.537 ns) 2.668 ns read_addr\[4\] 3 REG LCFF_X60_Y7_N27 6 " "Info: 3: + IC(1.024 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X60_Y7_N27; Fanout = 6; REG Node = 'read_addr\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "1.561 ns" { CLOCK_50~clkctrl read_addr[4] } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 57.20 % ) " "Info: Total cell delay = 1.526 ns ( 57.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.142 ns ( 42.80 % ) " "Info: Total interconnect delay = 1.142 ns ( 42.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.668 ns" { CLOCK_50 CLOCK_50~clkctrl read_addr[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.668 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl read_addr[4] } { 0.000ns 0.000ns 0.118ns 1.024ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.648 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.648 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "" { CLOCK_50 } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.107 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.107 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.004 ns) + CELL(0.537 ns) 2.648 ns count\[14\] 3 REG LCFF_X31_Y27_N3 3 " "Info: 3: + IC(1.004 ns) + CELL(0.537 ns) = 2.648 ns; Loc. = LCFF_X31_Y27_N3; Fanout = 3; REG Node = 'count\[14\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "1.541 ns" { CLOCK_50~clkctrl count[14] } "NODE_NAME" } "" } } { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 57.63 % ) " "Info: Total cell delay = 1.526 ns ( 57.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.122 ns ( 42.37 % ) " "Info: Total interconnect delay = 1.122 ns ( 42.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.648 ns" { CLOCK_50 CLOCK_50~clkctrl count[14] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.648 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl count[14] } { 0.000ns 0.000ns 0.118ns 1.004ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.668 ns" { CLOCK_50 CLOCK_50~clkctrl read_addr[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.668 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl read_addr[4] } { 0.000ns 0.000ns 0.118ns 1.024ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.648 ns" { CLOCK_50 CLOCK_50~clkctrl count[14] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.648 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl count[14] } { 0.000ns 0.000ns 0.118ns 1.004ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "6.633 ns" { count[14] LessThan~399 LessThan~401 LessThan~404 read_addr[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.633 ns" { count[14] LessThan~399 LessThan~401 LessThan~404 read_addr[4] } { 0.000ns 0.789ns 0.722ns 0.252ns 3.119ns } { 0.000ns 0.438ns 0.275ns 0.378ns 0.660ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.668 ns" { CLOCK_50 CLOCK_50~clkctrl read_addr[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.668 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl read_addr[4] } { 0.000ns 0.000ns 0.118ns 1.024ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.648 ns" { CLOCK_50 CLOCK_50~clkctrl count[14] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.648 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl count[14] } { 0.000ns 0.000ns 0.118ns 1.004ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[3\] register sld_hub:sld_hub_inst\|hub_tdo 139.86 MHz 7.15 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 139.86 MHz between source register \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[3\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 7.15 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.361 ns + Longest register register " "Info: + Longest register to register delay is 3.361 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[3\] 1 REG LCFF_X45_Y15_N7 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y15_N7; Fanout = 11; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } "NODE_NAME" } "" } } { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.296 ns) + CELL(0.438 ns) 1.734 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~13 2 COMB LCCOMB_X46_Y15_N28 2 " "Info: 2: + IC(1.296 ns) + CELL(0.438 ns) = 1.734 ns; Loc. = LCCOMB_X46_Y15_N28; Fanout = 2; COMB Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~13'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "1.734 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 } "NODE_NAME" } "" } } { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1020 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.270 ns) + CELL(0.150 ns) 2.154 ns sld_hub:sld_hub_inst\|hub_tdo~584 3 COMB LCCOMB_X46_Y15_N20 1 " "Info: 3: + IC(0.270 ns) + CELL(0.150 ns) = 2.154 ns; Loc. = LCCOMB_X46_Y15_N20; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~584'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "0.420 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~584 } "NODE_NAME" } "" } } { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.245 ns) 2.654 ns sld_hub:sld_hub_inst\|hub_tdo~587 4 COMB LCCOMB_X46_Y15_N22 1 " "Info: 4: + IC(0.255 ns) + CELL(0.245 ns) = 2.654 ns; Loc. = LCCOMB_X46_Y15_N22; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~587'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "0.500 ns" { sld_hub:sld_hub_inst|hub_tdo~584 sld_hub:sld_hub_inst|hub_tdo~587 } "NODE_NAME" } "" } } { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.376 ns) 3.277 ns sld_hub:sld_hub_inst\|hub_tdo~591 5 COMB LCCOMB_X46_Y15_N24 1 " "Info: 5: + IC(0.247 ns) + CELL(0.376 ns) = 3.277 ns; Loc. = LCCOMB_X46_Y15_N24; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~591'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "0.623 ns" { sld_hub:sld_hub_inst|hub_tdo~587 sld_hub:sld_hub_inst|hub_tdo~591 } "NODE_NAME" } "" } } { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.361 ns sld_hub:sld_hub_inst\|hub_tdo 6 REG LCFF_X46_Y15_N25 2 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 3.361 ns; Loc. = LCFF_X46_Y15_N25; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "0.084 ns" { sld_hub:sld_hub_inst|hub_tdo~591 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.293 ns ( 38.47 % ) " "Info: Total cell delay = 1.293 ns ( 38.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.068 ns ( 61.53 % ) " "Info: Total interconnect delay = 2.068 ns ( 61.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "3.361 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~584 sld_hub:sld_hub_inst|hub_tdo~587 sld_hub:sld_hub_inst|hub_tdo~591 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.361 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~584 sld_hub:sld_hub_inst|hub_tdo~587 sld_hub:sld_hub_inst|hub_tdo~591 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.296ns 0.270ns 0.255ns 0.247ns 0.000ns } { 0.000ns 0.438ns 0.150ns 0.245ns 0.376ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 3.824 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 3.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.273 ns) + CELL(0.000 ns) 2.273 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G11 125 " "Info: 2: + IC(2.273 ns) + CELL(0.000 ns) = 2.273 ns; Loc. = CLKCTRL_G11; Fanout = 125; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.273 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 3.824 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LCFF_X46_Y15_N25 2 " "Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 3.824 ns; Loc. = LCFF_X46_Y15_N25; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "1.551 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 14.04 % ) " "Info: Total cell delay = 0.537 ns ( 14.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.287 ns ( 85.96 % ) " "Info: Total interconnect delay = 3.287 ns ( 85.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 2.273ns 1.014ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 3.824 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 3.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.273 ns) + CELL(0.000 ns) 2.273 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G11 125 " "Info: 2: + IC(2.273 ns) + CELL(0.000 ns) = 2.273 ns; Loc. = CLKCTRL_G11; Fanout = 125; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "2.273 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.537 ns) 3.824 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[3\] 3 REG LCFF_X45_Y15_N7 11 " "Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 3.824 ns; Loc. = LCFF_X45_Y15_N7; Fanout = 11; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "1.551 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } "NODE_NAME" } "" } } { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 14.04 % ) " "Info: Total cell delay = 0.537 ns ( 14.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.287 ns ( 85.96 % ) " "Info: Total interconnect delay = 3.287 ns ( 85.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } { 0.000ns 2.273ns 1.014ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 2.273ns 1.014ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } { 0.000ns 2.273ns 1.014ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } } { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "3.361 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~584 sld_hub:sld_hub_inst|hub_tdo~587 sld_hub:sld_hub_inst|hub_tdo~591 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.361 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~584 sld_hub:sld_hub_inst|hub_tdo~587 sld_hub:sld_hub_inst|hub_tdo~591 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.296ns 0.270ns 0.255ns 0.247ns 0.000ns } { 0.000ns 0.438ns 0.150ns 0.245ns 0.376ns 0.084ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 2.273ns 1.014ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "part6" "UNKNOWN" "V1" "C:/altera/quartus51/exercise/lab8/part6/db/part6.quartus_db" { Floorplan "C:/altera/quartus51/exercise/lab8/part6/" "" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.824 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } { 0.000ns 2.273ns 1.014ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}