part6.hier_info

基于FPGA的CPU设计 VHDL 编写

|part6
CLOCK_50 => CLOCK_50~0.IN1
SW[0] => SW[0]~13.IN2
SW[1] => SW[1]~12.IN2
SW[2] => SW[2]~11.IN2
SW[3] => SW[3]~10.IN2
SW[4] => SW[4]~9.IN2
SW[5] => SW[5]~8.IN2
SW[6] => SW[6]~7.IN2
SW[7] => SW[7]~6.IN2
SW[8] => ~NO_FANOUT~
SW[9] => ~NO_FANOUT~
SW[10] => ~NO_FANOUT~
SW[11] => SW[11]~5.IN1
SW[12] => SW[12]~4.IN1
SW[13] => SW[13]~3.IN1
SW[14] => SW[14]~2.IN1
SW[15] => SW[15]~1.IN1
SW[16] => ~NO_FANOUT~
SW[17] => SW[17]~0.IN1
KEY[0] => count[24].ACLR
KEY[0] => count[23].ACLR
KEY[0] => count[22].ACLR
KEY[0] => count[21].ACLR
KEY[0] => count[20].ACLR
KEY[0] => count[19].ACLR
KEY[0] => count[18].ACLR
KEY[0] => count[17].ACLR
KEY[0] => count[16].ACLR
KEY[0] => count[15].ACLR
KEY[0] => count[14].ACLR
KEY[0] => count[13].ACLR
KEY[0] => count[12].ACLR
KEY[0] => count[11].ACLR
KEY[0] => count[10].ACLR
KEY[0] => count[9].ACLR
KEY[0] => count[8].ACLR
KEY[0] => count[7].ACLR
KEY[0] => count[6].ACLR
KEY[0] => count[5].ACLR
KEY[0] => count[4].ACLR
KEY[0] => count[3].ACLR
KEY[0] => count[2].ACLR
KEY[0] => count[1].ACLR
KEY[0] => count[0].ACLR
KEY[0] => read_addr[4].ACLR
KEY[0] => read_addr[3].ACLR
KEY[0] => read_addr[2].ACLR
KEY[0] => read_addr[1].ACLR
KEY[0] => read_addr[0].ACLR
KEY[0] => count[25].ACLR
KEY[1] => ~NO_FANOUT~
KEY[2] => ~NO_FANOUT~
KEY[3] => ~NO_FANOUT~
LEDG[0] <= SW[17]~0.DB_MAX_OUTPUT_PORT_TYPE
LEDG[1] <= <GND>
LEDG[2] <= <GND>
LEDG[3] <= <GND>
LEDG[4] <= <GND>
LEDG[5] <= <GND>
LEDG[6] <= <GND>
LEDG[7] <= <GND>
HEX0[0] <= SEG7_LUT:u2.oSEG
HEX0[1] <= SEG7_LUT:u2.oSEG
HEX0[2] <= SEG7_LUT:u2.oSEG
HEX0[3] <= SEG7_LUT:u2.oSEG
HEX0[4] <= SEG7_LUT:u2.oSEG
HEX0[5] <= SEG7_LUT:u2.oSEG
HEX0[6] <= SEG7_LUT:u2.oSEG
HEX1[0] <= SEG7_LUT:u1.oSEG
HEX1[1] <= SEG7_LUT:u1.oSEG
HEX1[2] <= SEG7_LUT:u1.oSEG
HEX1[3] <= SEG7_LUT:u1.oSEG
HEX1[4] <= SEG7_LUT:u1.oSEG
HEX1[5] <= SEG7_LUT:u1.oSEG
HEX1[6] <= SEG7_LUT:u1.oSEG
HEX2[0] <= SEG7_LUT:u4.oSEG
HEX2[1] <= SEG7_LUT:u4.oSEG
HEX2[2] <= SEG7_LUT:u4.oSEG
HEX2[3] <= SEG7_LUT:u4.oSEG
HEX2[4] <= SEG7_LUT:u4.oSEG
HEX2[5] <= SEG7_LUT:u4.oSEG
HEX2[6] <= SEG7_LUT:u4.oSEG
HEX3[0] <= SEG7_LUT:u3.oSEG
HEX3[1] <= SEG7_LUT:u3.oSEG
HEX3[2] <= SEG7_LUT:u3.oSEG
HEX3[3] <= SEG7_LUT:u3.oSEG
HEX3[4] <= SEG7_LUT:u3.oSEG
HEX3[5] <= SEG7_LUT:u3.oSEG
HEX3[6] <= SEG7_LUT:u3.oSEG
HEX4[0] <= SEG7_LUT:u6.oSEG
HEX4[1] <= SEG7_LUT:u6.oSEG
HEX4[2] <= SEG7_LUT:u6.oSEG
HEX4[3] <= SEG7_LUT:u6.oSEG
HEX4[4] <= SEG7_LUT:u6.oSEG
HEX4[5] <= SEG7_LUT:u6.oSEG
HEX4[6] <= SEG7_LUT:u6.oSEG
HEX5[0] <= SEG7_LUT:u5.oSEG
HEX5[1] <= SEG7_LUT:u5.oSEG
HEX5[2] <= SEG7_LUT:u5.oSEG
HEX5[3] <= SEG7_LUT:u5.oSEG
HEX5[4] <= SEG7_LUT:u5.oSEG
HEX5[5] <= SEG7_LUT:u5.oSEG
HEX5[6] <= SEG7_LUT:u5.oSEG
HEX6[0] <= SEG7_LUT:u8.oSEG
HEX6[1] <= SEG7_LUT:u8.oSEG
HEX6[2] <= SEG7_LUT:u8.oSEG
HEX6[3] <= SEG7_LUT:u8.oSEG
HEX6[4] <= SEG7_LUT:u8.oSEG
HEX6[5] <= SEG7_LUT:u8.oSEG
HEX6[6] <= SEG7_LUT:u8.oSEG
HEX7[0] <= SEG7_LUT:u7.oSEG
HEX7[1] <= SEG7_LUT:u7.oSEG
HEX7[2] <= SEG7_LUT:u7.oSEG
HEX7[3] <= SEG7_LUT:u7.oSEG
HEX7[4] <= SEG7_LUT:u7.oSEG
HEX7[5] <= SEG7_LUT:u7.oSEG
HEX7[6] <= SEG7_LUT:u7.oSEG


|part6|ramlpm:comb_42
address[0] => address[0]~4.IN1
address[1] => address[1]~3.IN1
address[2] => address[2]~2.IN1
address[3] => address[3]~1.IN1
address[4] => address[4]~0.IN1
clock => clock~0.IN1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
wren => wren~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|part6|ramlpm:comb_42|altsyncram:altsyncram_component
wren_a => altsyncram_2ih1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_2ih1:auto_generated.data_a[0]
data_a[1] => altsyncram_2ih1:auto_generated.data_a[1]
data_a[2] => altsyncram_2ih1:auto_generated.data_a[2]
data_a[3] => altsyncram_2ih1:auto_generated.data_a[3]
data_a[4] => altsyncram_2ih1:auto_generated.data_a[4]
data_a[5] => altsyncram_2ih1:auto_generated.data_a[5]
data_a[6] => altsyncram_2ih1:auto_generated.data_a[6]
data_a[7] => altsyncram_2ih1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_2ih1:auto_generated.address_a[0]
address_a[1] => altsyncram_2ih1:auto_generated.address_a[1]
address_a[2] => altsyncram_2ih1:auto_generated.address_a[2]
address_a[3] => altsyncram_2ih1:auto_generated.address_a[3]
address_a[4] => altsyncram_2ih1:auto_generated.address_a[4]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_2ih1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_2ih1:auto_generated.q_a[0]
q_a[1] <= altsyncram_2ih1:auto_generated.q_a[1]
q_a[2] <= altsyncram_2ih1:auto_generated.q_a[2]
q_a[3] <= altsyncram_2ih1:auto_generated.q_a[3]
q_a[4] <= altsyncram_2ih1:auto_generated.q_a[4]
q_a[5] <= altsyncram_2ih1:auto_generated.q_a[5]
q_a[6] <= altsyncram_2ih1:auto_generated.q_a[6]
q_a[7] <= altsyncram_2ih1:auto_generated.q_a[7]
q_b[0] <= <GND>


|part6|ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated
address_a[0] => altsyncram_cqa2:altsyncram1.address_a[0]
address_a[1] => altsyncram_cqa2:altsyncram1.address_a[1]
address_a[2] => altsyncram_cqa2:altsyncram1.address_a[2]
address_a[3] => altsyncram_cqa2:altsyncram1.address_a[3]
address_a[4] => altsyncram_cqa2:altsyncram1.address_a[4]
clock0 => altsyncram_cqa2:altsyncram1.clock0
data_a[0] => altsyncram_cqa2:altsyncram1.data_a[0]
data_a[1] => altsyncram_cqa2:altsyncram1.data_a[1]
data_a[2] => altsyncram_cqa2:altsyncram1.data_a[2]
data_a[3] => altsyncram_cqa2:altsyncram1.data_a[3]
data_a[4] => altsyncram_cqa2:altsyncram1.data_a[4]
data_a[5] => altsyncram_cqa2:altsyncram1.data_a[5]
data_a[6] => altsyncram_cqa2:altsyncram1.data_a[6]
data_a[7] => altsyncram_cqa2:altsyncram1.data_a[7]
q_a[0] <= altsyncram_cqa2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_cqa2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_cqa2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_cqa2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_cqa2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_cqa2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_cqa2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_cqa2:altsyncram1.q_a[7]
wren_a => altsyncram_cqa2:altsyncram1.wren_a


|part6|ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1
address_a[0] => altsyncram_pq12:altsyncram3.address_a[1]
address_a[1] => altsyncram_pq12:altsyncram3.address_a[2]
address_a[2] => altsyncram_pq12:altsyncram3.address_a[3]
address_a[3] => altsyncram_pq12:altsyncram3.address_a[4]
address_a[4] => altsyncram_pq12:altsyncram3.address_a[5]
address_b[0] => altsyncram_pq12:altsyncram3.address_b[1]
address_b[1] => altsyncram_pq12:altsyncram3.address_b[2]
address_b[2] => altsyncram_pq12:altsyncram3.address_b[3]
address_b[3] => altsyncram_pq12:altsyncram3.address_b[4]
address_b[4] => altsyncram_pq12:altsyncram3.address_b[5]
clock0 => altsyncram_pq12:altsyncram3.clock0
clock1 => altsyncram_pq12:altsyncram3.clock1
data_a[0] => altsyncram_pq12:altsyncram3.data_a[0]
data_a[1] => altsyncram_pq12:altsyncram3.data_a[1]
data_a[2] => altsyncram_pq12:altsyncram3.data_a[2]
data_a[3] => altsyncram_pq12:altsyncram3.data_a[3]
data_a[4] => altsyncram_pq12:altsyncram3.data_a[4]
data_a[5] => altsyncram_pq12:altsyncram3.data_a[5]
data_a[6] => altsyncram_pq12:altsyncram3.data_a[6]
data_a[7] => altsyncram_pq12:altsyncram3.data_a[7]
data_b[0] => altsyncram_pq12:altsyncram3.data_b[0]
data_b[1] => altsyncram_pq12:altsyncram3.data_b[1]
data_b[2] => altsyncram_pq12:altsyncram3.data_b[2]
data_b[3] => altsyncram_pq12:altsyncram3.data_b[3]
data_b[4] => altsyncram_pq12:altsyncram3.data_b[4]
data_b[5] => altsyncram_pq12:altsyncram3.data_b[5]
data_b[6] => altsyncram_pq12:altsyncram3.data_b[6]
data_b[7] => altsyncram_pq12:altsyncram3.data_b[7]
q_a[0] <= altsyncram_pq12:altsyncram3.q_a[0]
q_a[1] <= altsyncram_pq12:altsyncram3.q_a[1]
q_a[2] <= altsyncram_pq12:altsyncram3.q_a[2]
q_a[3] <= altsyncram_pq12:altsyncram3.q_a[3]
q_a[4] <= altsyncram_pq12:altsyncram3.q_a[4]
q_a[5] <= altsyncram_pq12:altsyncram3.q_a[5]
q_a[6] <= altsyncram_pq12:altsyncram3.q_a[6]
q_a[7] <= altsyncram_pq12:altsyncram3.q_a[7]
q_b[0] <= altsyncram_pq12:altsyncram3.q_b[0]
q_b[1] <= altsyncram_pq12:altsyncram3.q_b[1]
q_b[2] <= altsyncram_pq12:altsyncram3.q_b[2]
q_b[3] <= altsyncram_pq12:altsyncram3.q_b[3]
q_b[4] <= altsyncram_pq12:altsyncram3.q_b[4]
q_b[5] <= altsyncram_pq12:altsyncram3.q_b[5]
q_b[6] <= altsyncram_pq12:altsyncram3.q_b[6]
q_b[7] <= altsyncram_pq12:altsyncram3.q_b[7]
wren_a => altsyncram_pq12:altsyncram3.wren_a
wren_b => altsyncram_pq12:altsyncram3.wren_b


|part6|ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3
address_a[0] => ram_block4a0.PORTAADDR
address_a[0] => ram_block4a1.PORTAADDR
address_a[0] => ram_block4a2.PORTAADDR
address_a[0] => ram_block4a3.PORTAADDR
address_a[0] => ram_block4a4.PORTAADDR
address_a[0] => ram_block4a5.PORTAADDR
address_a[0] => ram_block4a6.PORTAADDR
address_a[0] => ram_block4a7.PORTAADDR
address_a[1] => ram_block4a0.PORTAADDR1
address_a[1] => ram_block4a1.PORTAADDR1
address_a[1] => ram_block4a2.PORTAADDR1
address_a[1] => ram_block4a3.PORTAADDR1
address_a[1] => ram_block4a4.PORTAADDR1
address_a[1] => ram_block4a5.PORTAADDR1
address_a[1] => ram_block4a6.PORTAADDR1
address_a[1] => ram_block4a7.PORTAADDR1
address_a[2] => ram_block4a0.PORTAADDR2
address_a[2] => ram_block4a1.PORTAADDR2
address_a[2] => ram_block4a2.PORTAADDR2
address_a[2] => ram_block4a3.PORTAADDR2
address_a[2] => ram_block4a4.PORTAADDR2
address_a[2] => ram_block4a5.PORTAADDR2
address_a[2] => ram_block4a6.PORTAADDR2
address_a[2] => ram_block4a7.PORTAADDR2
address_a[3] => ram_block4a0.PORTAADDR3
address_a[3] => ram_block4a1.PORTAADDR3
address_a[3] => ram_block4a2.PORTAADDR3
address_a[3] => ram_block4a3.PORTAADDR3
address_a[3] => ram_block4a4.PORTAADDR3
address_a[3] => ram_block4a5.PORTAADDR3
address_a[3] => ram_block4a6.PORTAADDR3
address_a[3] => ram_block4a7.PORTAADDR3
address_a[4] => ram_block4a0.PORTAADDR4
address_a[4] => ram_block4a1.PORTAADDR4
address_a[4] => ram_block4a2.PORTAADDR4
address_a[4] => ram_block4a3.PORTAADDR4
address_a[4] => ram_block4a4.PORTAADDR4
address_a[4] => ram_block4a5.PORTAADDR4
address_a[4] => ram_block4a6.PORTAADDR4
address_a[4] => ram_block4a7.PORTAADDR4
address_a[5] => ram_block4a0.PORTAADDR5
address_a[5] => ram_block4a1.PORTAADDR5
address_a[5] => ram_block4a2.PORTAADDR5
address_a[5] => ram_block4a3.PORTAADDR5
address_a[5] => ram_block4a4.PORTAADDR5
address_a[5] => ram_block4a5.PORTAADDR5
address_a[5] => ram_block4a6.PORTAADDR5
address_a[5] => ram_block4a7.PORTAADDR5
address_b[0] => ram_block4a0.PORTBADDR
address_b[0] => ram_block4a1.PORTBADDR
address_b[0] => ram_block4a2.PORTBADDR
address_b[0] => ram_block4a3.PORTBADDR
address_b[0] => ram_block4a4.PORTBADDR
address_b[0] => ram_block4a5.PORTBADDR
address_b[0] => ram_block4a6.PORTBADDR
address_b[0] => ram_block4a7.PORTBADDR
address_b[1] => ram_block4a0.PORTBADDR1
address_b[1] => ram_block4a1.PORTBADDR1
address_b[1] => ram_block4a2.PORTBADDR1
address_b[1] => ram_block4a3.PORTBADDR1
address_b[1] => ram_block4a4.PORTBADDR1
address_b[1] => ram_block4a5.PORTBADDR1
address_b[1] => ram_block4a6.PORTBADDR1
address_b[1] => ram_block4a7.PORTBADDR1
address_b[2] => ram_block4a0.PORTBADDR2
address_b[2] => ram_block4a1.PORTBADDR2
address_b[2] => ram_block4a2.PORTBADDR2
address_b[2] => ram_block4a3.PORTBADDR2
address_b[2] => ram_block4a4.PORTBADDR2
address_b[2] => ram_block4a5.PORTBADDR2
address_b[2] => ram_block4a6.PORTBADDR2
address_b[2] => ram_block4a7.PORTBADDR2
address_b[3] => ram_block4a0.PORTBADDR3
address_b[3] => ram_block4a1.PORTBADDR3
address_b[3] => ram_block4a2.PORTBADDR3
address_b[3] => ram_block4a3.PORTBADDR3
address_b[3] => ram_block4a4.PORTBADDR3
address_b[3] => ram_block4a5.PORTBADDR3
address_b[3] => ram_block4a6.PORTBADDR3
address_b[3] => ram_block4a7.PORTBADDR3
address_b[4] => ram_block4a0.PORTBADDR4
address_b[4] => ram_block4a1.PORTBADDR4
address_b[4] => ram_block4a2.PORTBADDR4
address_b[4] => ram_block4a3.PORTBADDR4
address_b[4] => ram_block4a4.PORTBADDR4
address_b[4] => ram_block4a5.PORTBADDR4
address_b[4] => ram_block4a6.PORTBADDR4
address_b[4] => ram_block4a7.PORTBADDR4
address_b[5] => ram_block4a0.PORTBADDR5
address_b[5] => ram_block4a1.PORTBADDR5
address_b[5] => ram_block4a2.PORTBADDR5
address_b[5] => ram_block4a3.PORTBADDR5
address_b[5] => ram_block4a4.PORTBADDR5
address_b[5] => ram_block4a5.PORTBADDR5
address_b[5] => ram_block4a6.PORTBADDR5
address_b[5] => ram_block4a7.PORTBADDR5
clock0 => ram_block4a0.CLK0
clock0 => ram_block4a1.CLK0
clock0 => ram_block4a2.CLK0
clock0 => ram_block4a3.CLK0
clock0 => ram_block4a4.CLK0
clock0 => ram_block4a5.CLK0
clock0 => ram_block4a6.CLK0
clock0 => ram_block4a7.CLK0
clock1 => ram_block4a0.CLK1
clock1 => ram_block4a1.CLK1
clock1 => ram_block4a2.CLK1
clock1 => ram_block4a3.CLK1
clock1 => ram_block4a4.CLK1
clock1 => ram_block4a5.CLK1
clock1 => ram_block4a6.CLK1
clock1 => ram_block4a7.CLK1
data_a[0] => ram_block4a0.PORTADATAIN
data_a[1] => ram_block4a1.PORTADATAIN