part6.map.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_pq12.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pq12.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_pq12 " "Info: Found entity 1: altsyncram_pq12" {  } { { "db/altsyncram_pq12.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_pq12.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_pq12 ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3 " "Info: Elaborating entity \"altsyncram_pq12\" for hierarchy \"ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|altsyncram_cqa2:altsyncram1\|altsyncram_pq12:altsyncram3\"" {  } { { "db/altsyncram_cqa2.tdf" "altsyncram3" { Text "C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_cqa2.tdf" 40 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../libraries/megafunctions/sld_mod_ram_rom.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file ../../../libraries/megafunctions/sld_mod_ram_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mod_ram_rom_pack " "Info: Found design unit 1: sld_mod_ram_rom_pack" {  } { { "../../../libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_mod_ram_rom-rtl " "Info: Found design unit 2: sld_mod_ram_rom-rtl" {  } { { "../../../libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 72 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mod_ram_rom " "Info: Found entity 1: sld_mod_ram_rom" {  } { { "../../../libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_2ih1.tdf" "mgl_prim2" { Text "C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_2ih1.tdf" 37 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../../libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "../../../libraries/megafunctions/sld_rom_sr.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "../../../libraries/megafunctions/sld_rom_sr.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr " "Info: Elaborating entity \"sld_rom_sr\" for hierarchy \"ramlpm:comb_42\|altsyncram:altsyncram_component\|altsyncram_2ih1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\"" {  } { { "../../../libraries/megafunctions/sld_mod_ram_rom.vhd" "\\ram_rom_logic_gen:name_gen:info_rom_sr" { Text "C:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 635 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "SEG7_LUT.v 1 1 " "Warning: Using design file SEG7_LUT.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Info: Found entity 1: SEG7_LUT" {  } { { "SEG7_LUT.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/SEG7_LUT.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT SEG7_LUT:u1 " "Info: Elaborating entity \"SEG7_LUT\" for hierarchy \"SEG7_LUT:u1\"" {  } { { "part6.v" "u1" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 49 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "iDIG u7 1 4 " "Warning: Port \"iDIG\" on the entity instantiation of \"u7\" is connected to a signal of width 1. The formal width of the signal in the module is 4.  Extra bits will be driven by GND." {  } { { "part6.v" "u7" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 55 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "iDIG u3 1 4 " "Warning: Port \"iDIG\" on the entity instantiation of \"u3\" is connected to a signal of width 1. The formal width of the signal in the module is 4.  Extra bits will be driven by GND." {  } { { "part6.v" "u3" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 51 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file ../../../libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1018 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1003 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_shiftreg.tdf" 37 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_decode.tdf" 62 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_rpe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_rpe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_rpe " "Info: Found entity 1: decode_rpe" {  } { { "db/decode_rpe.tdf" "" { Text "C:/altera/quartus51/exercise/lab8/part6/db/decode_rpe.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../../libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "../../../libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "../../../libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "../../../libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[1\] GND " "Warning: Pin \"LEDG\[1\]\" stuck at GND" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[2\] GND " "Warning: Pin \"LEDG\[2\]\" stuck at GND" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[3\] GND " "Warning: Pin \"LEDG\[3\]\" stuck at GND" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[4\] GND " "Warning: Pin \"LEDG\[4\]\" stuck at GND" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[5\] GND " "Warning: Pin \"LEDG\[5\]\" stuck at GND" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[6\] GND " "Warning: Pin \"LEDG\[6\]\" stuck at GND" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[7\] GND " "Warning: Pin \"LEDG\[7\]\" stuck at GND" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[1\] GND " "Warning: Pin \"HEX3\[1\]\" stuck at GND" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[2\] GND " "Warning: Pin \"HEX3\[2\]\" stuck at GND" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[6\] VCC " "Warning: Pin \"HEX3\[6\]\" stuck at VCC" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX7\[1\] GND " "Warning: Pin \"HEX7\[1\]\" stuck at GND" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX7\[2\] GND " "Warning: Pin \"HEX7\[2\]\" stuck at GND" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX7\[6\] VCC " "Warning: Pin \"HEX7\[6\]\" stuck at VCC" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "7 " "Warning: Design contains 7 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[8\] " "Warning: No output dependent on input pin \"SW\[8\]\"" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[9\] " "Warning: No output dependent on input pin \"SW\[9\]\"" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[10\] " "Warning: No output dependent on input pin \"SW\[10\]\"" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW\[16\] " "Warning: No output dependent on input pin \"SW\[16\]\"" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "Warning: No output dependent on input pin \"KEY\[1\]\"" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "Warning: No output dependent on input pin \"KEY\[2\]\"" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "KEY\[3\] " "Warning: No output dependent on input pin \"KEY\[3\]\"" {  } { { "part6.v" "" { Text "C:/altera/quartus51/exercise/lab8/part6/part6.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "351 " "Info: Implemented 351 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "26 " "Info: Implemented 26 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "65 " "Info: Implemented 65 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "251 " "Info: Implemented 251 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 35 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 19 14:59:16 2007 " "Info: Processing ended: Thu Apr 19 14:59:16 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}