part6.map.rpt

基于FPGA的CPU设计 VHDL 编写

; device_family            ; Cyclone II                       ; Untyped ;
; n_nodes                  ; 1                                ; Untyped ;
; n_sel_bits               ; 1                                ; Untyped ;
; n_node_ir_bits           ; 5                                ; Untyped ;
; node_info                ; 00001000000110000110111000000000 ; Binary  ;
+--------------------------+----------------------------------+---------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------+
; In-System Memory Content Editor Settings                                                                                                  ;
+----------------+-------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Instance Index ; Instance ID ; Width ; Depth ; Mode       ; Hierarchy Location                                                            ;
+----------------+-------------+-------+-------+------------+-------------------------------------------------------------------------------+
; 0              ; 32x8        ; 8     ; 32    ; Read/Write ; ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated ;
+----------------+-------------+-------+-------+------------+-------------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/quartus51/exercise/lab8/part6/part6.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Apr 19 14:59:08 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part6 -c part6
Info: Found 1 design units, including 1 entities, in source file part6.v
    Info: Found entity 1: part6
Info: Elaborating entity "part6" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at part6.v(28): truncated value with size 32 to match size of target (26)
Warning (10230): Verilog HDL assignment warning at part6.v(33): truncated value with size 32 to match size of target (5)
Warning (10034): Output port "LEDG[7]" at part6.v(7) has no driver
Warning (10034): Output port "LEDG[6]" at part6.v(7) has no driver
Warning (10034): Output port "LEDG[5]" at part6.v(7) has no driver
Warning (10034): Output port "LEDG[4]" at part6.v(7) has no driver
Warning (10034): Output port "LEDG[3]" at part6.v(7) has no driver
Warning (10034): Output port "LEDG[2]" at part6.v(7) has no driver
Warning (10034): Output port "LEDG[1]" at part6.v(7) has no driver
Warning: Using design file ramlpm.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ramlpm
Info: Elaborating entity "ramlpm" for hierarchy "ramlpm:comb_42"
Info: Found 1 design units, including 1 entities, in source file ../../../libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "ramlpm:comb_42|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_2ih1.tdf
    Info: Found entity 1: altsyncram_2ih1
Info: Elaborating entity "altsyncram_2ih1" for hierarchy "ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_cqa2.tdf
    Info: Found entity 1: altsyncram_cqa2
Info: Elaborating entity "altsyncram_cqa2" for hierarchy "ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pq12.tdf
    Info: Found entity 1: altsyncram_pq12
Info: Elaborating entity "altsyncram_pq12" for hierarchy "ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3"
Info: Found 3 design units, including 1 entities, in source file ../../../libraries/megafunctions/sld_mod_ram_rom.vhd
    Info: Found design unit 1: sld_mod_ram_rom_pack
    Info: Found design unit 2: sld_mod_ram_rom-rtl
    Info: Found entity 1: sld_mod_ram_rom
Info: Elaborating entity "sld_mod_ram_rom" for hierarchy "ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|sld_mod_ram_rom:mgl_prim2"
Info: Found 2 design units, including 1 entities, in source file ../../../libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Elaborating entity "sld_rom_sr" for hierarchy "ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr"
Warning: Using design file SEG7_LUT.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SEG7_LUT
Info: Elaborating entity "SEG7_LUT" for hierarchy "SEG7_LUT:u1"
Warning: Port "iDIG" on the entity instantiation of "u7" is connected to a signal of width 1. The formal width of the signal in the module is 4.  Extra bits will be driven by GND.
Warning: Port "iDIG" on the entity instantiation of "u3" is connected to a signal of width 1. The formal width of the signal in the module is 4.  Extra bits will be driven by GND.
Info: Found 6 design units, including 2 entities, in source file ../../../libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Found 1 design units, including 1 entities, in source file ../../../libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 1 design units, including 1 entities, in source file ../../../libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Found 1 design units, including 1 entities, in source file db/decode_rpe.tdf
    Info: Found entity 1: decode_rpe
Info: Found 2 design units, including 1 entities, in source file ../../../libraries/megafunctions/sld_dffex.vhd
    Info: Found design unit 1: sld_dffex-DFFEX
    Info: Found entity 1: sld_dffex
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "LEDG[1]" stuck at GND
    Warning: Pin "LEDG[2]" stuck at GND
    Warning: Pin "LEDG[3]" stuck at GND
    Warning: Pin "LEDG[4]" stuck at GND
    Warning: Pin "LEDG[5]" stuck at GND
    Warning: Pin "LEDG[6]" stuck at GND
    Warning: Pin "LEDG[7]" stuck at GND
    Warning: Pin "HEX3[1]" stuck at GND
    Warning: Pin "HEX3[2]" stuck at GND
    Warning: Pin "HEX3[6]" stuck at VCC
    Warning: Pin "HEX7[1]" stuck at GND
    Warning: Pin "HEX7[2]" stuck at GND
    Warning: Pin "HEX7[6]" stuck at VCC
Warning: Design contains 7 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "SW[8]"
    Warning: No output dependent on input pin "SW[9]"
    Warning: No output dependent on input pin "SW[10]"
    Warning: No output dependent on input pin "SW[16]"
    Warning: No output dependent on input pin "KEY[1]"
    Warning: No output dependent on input pin "KEY[2]"
    Warning: No output dependent on input pin "KEY[3]"
Info: Implemented 351 device resources after synthesis - the final resource count might be different
    Info: Implemented 26 input pins
    Info: Implemented 65 output pins
    Info: Implemented 251 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 35 warnings
    Info: Processing ended: Thu Apr 19 14:59:16 2007
    Info: Elapsed time: 00:00:08