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📄 part6.map.rpt

📁 基于FPGA的CPU设计 VHDL 编写
💻 RPT
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+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+----------------------+--------------------------+
; Name                 ; Setting                  ;
+----------------------+--------------------------+
; CYCLONEII_SAFE_WRITE ; RESTRUCTURE              ;
+----------------------+--------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                      ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+
; part6.v                          ; yes             ; User Verilog HDL File        ; C:/altera/quartus51/exercise/lab8/part6/part6.v                   ;
; ramlpm.v                         ; yes             ; Other                        ; C:/altera/quartus51/exercise/lab8/part6/ramlpm.v                  ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/lpm_decode.inc        ;
; aglobal51.inc                    ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/aglobal51.inc         ;
; altsyncram.inc                   ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/altsyncram.inc        ;
; a_rdenreg.inc                    ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/altram.inc            ;
; altdpram.inc                     ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                     ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_2ih1.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_2ih1.tdf    ;
; db/altsyncram_cqa2.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_cqa2.tdf    ;
; db/altsyncram_pq12.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/altera/quartus51/exercise/lab8/part6/db/altsyncram_pq12.tdf    ;
; sld_mod_ram_rom.vhd              ; yes             ; Encrypted Megafunction       ; c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd   ;
; sld_rom_sr.vhd                   ; yes             ; Encrypted Megafunction       ; c:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd        ;
; SEG7_LUT.v                       ; yes             ; Other                        ; C:/altera/quartus51/exercise/lab8/part6/SEG7_LUT.v                ;
; sld_hub.vhd                      ; yes             ; Encrypted Megafunction       ; c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd           ;
; lpm_shiftreg.tdf                 ; yes             ; Megafunction                 ; c:/altera/quartus51/libraries/megafunctions/lpm_shiftreg.tdf      ;
; lpm_constant.inc                 ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/lpm_constant.inc      ;
; dffeea.inc                       ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/dffeea.inc            ;
; lpm_decode.tdf                   ; yes             ; Megafunction                 ; c:/altera/quartus51/libraries/megafunctions/lpm_decode.tdf        ;
; declut.inc                       ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/declut.inc            ;
; altshift.inc                     ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/altshift.inc          ;
; lpm_compare.inc                  ; yes             ; Other                        ; c:/altera/quartus51/libraries/megafunctions/lpm_compare.inc       ;
; db/decode_rpe.tdf                ; yes             ; Auto-Generated Megafunction  ; C:/altera/quartus51/exercise/lab8/part6/db/decode_rpe.tdf         ;
; sld_dffex.vhd                    ; yes             ; Encrypted Megafunction       ; c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd         ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+


+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                            ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Total combinational functions               ; 231                      ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 112                      ;
;     -- 3 input functions                    ; 42                       ;
;     -- <=2 input functions                  ; 77                       ;
;         -- Combinational cells for routing  ; 0                        ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 187                      ;
;     -- arithmetic mode                      ; 44                       ;
; Total registers                             ; 133                      ;
; I/O pins                                    ; 87                       ;
; Total memory bits                           ; 512                      ;
; Maximum fan-out node                        ; altera_internal_jtag~TDO ;
; Maximum fan-out                             ; 132                      ;
; Total fan-out                               ; 1375                     ;
; Average fan-out                             ; 2.96                     ;
+---------------------------------------------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                 ;
+---------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                          ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                               ;
+---------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |part6                                                              ; 231 (43)          ; 133 (31)     ; 512         ; 0            ; 0       ; 0         ; 87   ; 0            ; |part6                                                                                                                                                            ;
;    |SEG7_LUT:u1|                                                    ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|SEG7_LUT:u1                                                                                                                                                ;
;    |SEG7_LUT:u2|                                                    ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|SEG7_LUT:u2                                                                                                                                                ;
;    |SEG7_LUT:u4|                                                    ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|SEG7_LUT:u4                                                                                                                                                ;
;    |SEG7_LUT:u5|                                                    ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|SEG7_LUT:u5                                                                                                                                                ;
;    |SEG7_LUT:u6|                                                    ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|SEG7_LUT:u6                                                                                                                                                ;
;    |SEG7_LUT:u8|                                                    ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|SEG7_LUT:u8                                                                                                                                                ;
;    |ramlpm:comb_42|                                                 ; 55 (0)            ; 32 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|ramlpm:comb_42                                                                                                                                             ;
;       |altsyncram:altsyncram_component|                             ; 55 (0)            ; 32 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|ramlpm:comb_42|altsyncram:altsyncram_component                                                                                                             ;
;          |altsyncram_2ih1:auto_generated|                           ; 55 (0)            ; 32 (0)       ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated                                                                              ;
;             |altsyncram_cqa2:altsyncram1|                           ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1                                                  ;
;                |altsyncram_pq12:altsyncram3|                        ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3                      ;
;             |sld_mod_ram_rom:mgl_prim2|                             ; 55 (31)           ; 32 (23)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|sld_mod_ram_rom:mgl_prim2                                                    ;
;                |sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr| ; 24 (24)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr ;
;    |sld_hub:sld_hub_inst|                                           ; 91 (36)           ; 70 (7)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst                                                                                                                                       ;
;       |lpm_decode:instruction_decoder|                              ; 5 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder                                                                                                        ;
;          |decode_rpe:auto_generated|                                ; 5 (5)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated                                                                              ;
;       |lpm_shiftreg:jtag_ir_register|                               ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register                                                                                                         ;
;       |sld_dffex:BROADCAST|                                         ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst|sld_dffex:BROADCAST                                                                                                                   ;
;       |sld_dffex:IRF_ENA_0|                                         ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0                                                                                                                   ;
;       |sld_dffex:IRF_ENA|                                           ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA                                                                                                                     ;
;       |sld_dffex:IRSR|                                              ; 3 (3)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst|sld_dffex:IRSR                                                                                                                        ;
;       |sld_dffex:RESET|                                             ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst|sld_dffex:RESET                                                                                                                       ;
;       |sld_dffex:\GEN_IRF:1:IRF|                                    ; 1 (1)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF                                                                                                              ;
;       |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|                           ; 0 (0)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF                                                                                                     ;
;       |sld_jtag_state_machine:jtag_state_machine|                   ; 20 (20)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine                                                                                             ;
;       |sld_rom_sr:HUB_INFO_REG|                                     ; 21 (21)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part6|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG                                                                                                               ;
+---------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                  ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+---------------------+
; Name                                                                                                                                             ; Type ; Mode           ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF                 ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+---------------------+
; ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ALTSYNCRAM ; M4K  ; True Dual Port ; 64           ; 8            ; 64           ; 8            ; 512  ; ./db/ramlpm_mod.mif ;
+--------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+---------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 133   ;
; Number of registers using Synchronous Clear  ; 49    ;
; Number of registers using Synchronous Load   ; 5     ;
; Number of registers using Asynchronous Clear ; 84    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 69    ;
; Number of registers using Preset             ; 0     ;

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