ramlpm.mif

基于FPGA的CPU设计 VHDL 编写

WIDTH=8;
DEPTH=32;

ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;

CONTENT BEGIN

0:0;
1:1;
2:2;
3:3;
4:4;
5:5;
6:6;
7:7;
8:8;
9:9;
A:A;
B:B;
C:C;
D:D;
E:E;
F:F;
10:10;
11:11;
12:12;
13:13;
14:14;
15:15;
16:16;
17:17;
18:18;
19:19;
1A:1A;
1B:1B;
1C:1C;
1D:1D;
1E:1E;
1F:1F;

END;

/*END OF FILE*/