part6.v

基于FPGA的CPU设计 VHDL 编写

module part6(CLOCK_50,SW,KEY,LEDG,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7);

input			CLOCK_50;
input	[17:0]	SW;
input	[3:0]	KEY;
output	[6:0]	HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
output	[7:0]	LEDG;

wire			RST_N;
wire	[7:0]	Q;

reg		[25:0]	count;
reg		[4:0]	read_addr;

assign	RST_N	=	KEY[0];
assign	LEDG[0]	=	SW[17];

always@(posedge CLOCK_50 or negedge RST_N)
begin
	if(!RST_N)
	begin
		count		<=	0;
		read_addr	<=	0;
	end
	else
	begin
		if(count<26'h2faf080)
		count	<=	count + 1;
		else
		begin
			count	<=	0;
			if(read_addr<32)
			read_addr	<=	read_addr + 1;
			else
			read_addr	<=	0;
		end
	end
end

		
ramlpm (
		.address(read_addr),
		.clock(CLOCK_50),
		.data(SW[7:0]),
		.wren(SW[17]),
		.q(Q));


SEG7_LUT	u1(.oSEG(HEX1),.iDIG(Q[7:4]));
SEG7_LUT	u2(.oSEG(HEX0),.iDIG(Q[3:0]));
SEG7_LUT	u3(.oSEG(HEX3),.iDIG(read_addr[4]));
SEG7_LUT	u4(.oSEG(HEX2),.iDIG(read_addr[3:0]));
SEG7_LUT	u5(.oSEG(HEX5),.iDIG(SW[7:4]));
SEG7_LUT	u6(.oSEG(HEX4),.iDIG(SW[3:0]));
SEG7_LUT	u7(.oSEG(HEX7),.iDIG(SW[15]));
SEG7_LUT	u8(.oSEG(HEX6),.iDIG(SW[14:11]));

endmodule