part6.tan.rpt

基于FPGA的CPU设计 VHDL 编写

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                  ; To                                                                                                                                                              ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 4.489 ns                         ; SW[17]                                                                                                                                                                ; ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg ; --                           ; CLOCK_50                     ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 13.501 ns                        ; ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_address_reg5 ; HEX0[0]                                                                                                                                                         ; CLOCK_50                     ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 10.623 ns                        ; SW[13]                                                                                                                                                                ; HEX6[0]                                                                                                                                                         ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 1.184 ns                         ; altera_internal_jtag                                                                                                                                                  ; sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5]                                                                                                                        ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 139.86 MHz ( period = 7.150 ns ) ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]                                                                                               ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                                    ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLOCK_50'                     ; N/A   ; None          ; 146.48 MHz ( period = 6.827 ns ) ; count[14]                                                                                                                                                             ; read_addr[0]                                                                                                                                                    ; CLOCK_50                     ; CLOCK_50                     ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                                                       ;                                                                                                                                                                 ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;