part6.tan.summary

来自「基于FPGA的CPU设计 VHDL 编写」· SUMMARY 代码 · 共 77 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.489 ns
From           : SW[17]
To             : ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_we_reg
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.501 ns
From           : ramlpm:comb_42|altsyncram:altsyncram_component|altsyncram_2ih1:auto_generated|altsyncram_cqa2:altsyncram1|altsyncram_pq12:altsyncram3|ram_block4a0~porta_address_reg5
To             : HEX0[0]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.623 ns
From           : SW[13]
To             : HEX6[0]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.184 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 139.86 MHz ( period = 7.150 ns )
From           : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : N/A
Required Time  : None
Actual Time    : 146.48 MHz ( period = 6.827 ns )
From           : count[14]
To             : read_addr[0]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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