📄 part4.sim.rpt
字号:
; |part4|LEDG[1] ; |part4|LEDG[1] ; padio ;
; |part4|LEDG[2] ; |part4|LEDG[2] ; padio ;
; |part4|LEDG[3] ; |part4|LEDG[3] ; padio ;
; |part4|LEDG[4] ; |part4|LEDG[4] ; padio ;
; |part4|LEDG[5] ; |part4|LEDG[5] ; padio ;
; |part4|LEDG[6] ; |part4|LEDG[6] ; padio ;
; |part4|LEDG[7] ; |part4|LEDG[7] ; padio ;
; |part4|HEX0[0] ; |part4|HEX0[0] ; padio ;
; |part4|HEX0[1] ; |part4|HEX0[1] ; padio ;
; |part4|HEX0[2] ; |part4|HEX0[2] ; padio ;
; |part4|HEX0[3] ; |part4|HEX0[3] ; padio ;
; |part4|HEX0[4] ; |part4|HEX0[4] ; padio ;
; |part4|HEX0[5] ; |part4|HEX0[5] ; padio ;
; |part4|HEX0[6] ; |part4|HEX0[6] ; padio ;
; |part4|HEX1[0] ; |part4|HEX1[0] ; padio ;
; |part4|HEX1[1] ; |part4|HEX1[1] ; padio ;
; |part4|HEX1[2] ; |part4|HEX1[2] ; padio ;
; |part4|HEX1[3] ; |part4|HEX1[3] ; padio ;
; |part4|HEX1[4] ; |part4|HEX1[4] ; padio ;
; |part4|HEX1[5] ; |part4|HEX1[5] ; padio ;
; |part4|HEX1[6] ; |part4|HEX1[6] ; padio ;
; |part4|HEX2[0] ; |part4|HEX2[0] ; padio ;
; |part4|HEX2[1] ; |part4|HEX2[1] ; padio ;
; |part4|HEX2[2] ; |part4|HEX2[2] ; padio ;
; |part4|HEX2[3] ; |part4|HEX2[3] ; padio ;
; |part4|HEX2[4] ; |part4|HEX2[4] ; padio ;
; |part4|HEX2[5] ; |part4|HEX2[5] ; padio ;
; |part4|HEX2[6] ; |part4|HEX2[6] ; padio ;
; |part4|HEX3[0] ; |part4|HEX3[0] ; padio ;
; |part4|HEX3[1] ; |part4|HEX3[1] ; padio ;
; |part4|HEX3[2] ; |part4|HEX3[2] ; padio ;
; |part4|HEX3[3] ; |part4|HEX3[3] ; padio ;
; |part4|HEX3[4] ; |part4|HEX3[4] ; padio ;
; |part4|HEX3[5] ; |part4|HEX3[5] ; padio ;
; |part4|HEX3[6] ; |part4|HEX3[6] ; padio ;
; |part4|HEX4[0] ; |part4|HEX4[0] ; padio ;
; |part4|HEX4[1] ; |part4|HEX4[1] ; padio ;
; |part4|HEX4[2] ; |part4|HEX4[2] ; padio ;
; |part4|HEX4[3] ; |part4|HEX4[3] ; padio ;
; |part4|HEX4[4] ; |part4|HEX4[4] ; padio ;
; |part4|HEX4[5] ; |part4|HEX4[5] ; padio ;
; |part4|HEX4[6] ; |part4|HEX4[6] ; padio ;
; |part4|HEX5[0] ; |part4|HEX5[0] ; padio ;
; |part4|HEX5[1] ; |part4|HEX5[1] ; padio ;
; |part4|HEX5[2] ; |part4|HEX5[2] ; padio ;
; |part4|HEX5[3] ; |part4|HEX5[3] ; padio ;
; |part4|HEX5[4] ; |part4|HEX5[4] ; padio ;
; |part4|HEX5[5] ; |part4|HEX5[5] ; padio ;
; |part4|HEX5[6] ; |part4|HEX5[6] ; padio ;
; |part4|HEX6[0] ; |part4|HEX6[0] ; padio ;
; |part4|HEX6[1] ; |part4|HEX6[1] ; padio ;
; |part4|HEX6[2] ; |part4|HEX6[2] ; padio ;
; |part4|HEX6[3] ; |part4|HEX6[3] ; padio ;
; |part4|HEX6[4] ; |part4|HEX6[4] ; padio ;
; |part4|HEX6[5] ; |part4|HEX6[5] ; padio ;
; |part4|HEX6[6] ; |part4|HEX6[6] ; padio ;
; |part4|HEX7[0] ; |part4|HEX7[0] ; padio ;
; |part4|HEX7[1] ; |part4|HEX7[1] ; padio ;
; |part4|HEX7[2] ; |part4|HEX7[2] ; padio ;
; |part4|HEX7[3] ; |part4|HEX7[3] ; padio ;
; |part4|HEX7[4] ; |part4|HEX7[4] ; padio ;
; |part4|HEX7[5] ; |part4|HEX7[5] ; padio ;
; |part4|HEX7[6] ; |part4|HEX7[6] ; padio ;
; |part4|SRAM_ADDR[0] ; |part4|SRAM_ADDR[0] ; padio ;
; |part4|SRAM_ADDR[1] ; |part4|SRAM_ADDR[1] ; padio ;
; |part4|SRAM_ADDR[2] ; |part4|SRAM_ADDR[2] ; padio ;
; |part4|SRAM_ADDR[3] ; |part4|SRAM_ADDR[3] ; padio ;
; |part4|SRAM_ADDR[4] ; |part4|SRAM_ADDR[4] ; padio ;
; |part4|SRAM_ADDR[5] ; |part4|SRAM_ADDR[5] ; padio ;
; |part4|SRAM_ADDR[6] ; |part4|SRAM_ADDR[6] ; padio ;
; |part4|SRAM_ADDR[7] ; |part4|SRAM_ADDR[7] ; padio ;
; |part4|SRAM_ADDR[8] ; |part4|SRAM_ADDR[8] ; padio ;
; |part4|SRAM_ADDR[9] ; |part4|SRAM_ADDR[9] ; padio ;
; |part4|SRAM_ADDR[10] ; |part4|SRAM_ADDR[10] ; padio ;
; |part4|SRAM_ADDR[11] ; |part4|SRAM_ADDR[11] ; padio ;
; |part4|SRAM_ADDR[12] ; |part4|SRAM_ADDR[12] ; padio ;
; |part4|SRAM_ADDR[13] ; |part4|SRAM_ADDR[13] ; padio ;
; |part4|SRAM_ADDR[14] ; |part4|SRAM_ADDR[14] ; padio ;
; |part4|SRAM_ADDR[15] ; |part4|SRAM_ADDR[15] ; padio ;
; |part4|SRAM_ADDR[16] ; |part4|SRAM_ADDR[16] ; padio ;
; |part4|SRAM_ADDR[17] ; |part4|SRAM_ADDR[17] ; padio ;
; |part4|SRAM_UB_N ; |part4|SRAM_UB_N ; padio ;
; |part4|SRAM_LB_N ; |part4|SRAM_LB_N ; padio ;
; |part4|SRAM_WE_N ; |part4|SRAM_WE_N ; padio ;
; |part4|SRAM_CE_N ; |part4|SRAM_CE_N ; padio ;
; |part4|SRAM_OE_N ; |part4|SRAM_OE_N ; padio ;
; |part4|oDATA[0] ; |part4|oDATA[0] ; combout ;
; |part4|oDATA[0] ; |part4|SRAM_DQ[0]~output ; padio ;
; |part4|oDATA[1] ; |part4|oDATA[1] ; combout ;
; |part4|oDATA[1] ; |part4|SRAM_DQ[1]~output ; padio ;
; |part4|oDATA[2] ; |part4|oDATA[2] ; combout ;
; |part4|oDATA[2] ; |part4|SRAM_DQ[2]~output ; padio ;
; |part4|oDATA[3] ; |part4|oDATA[3] ; combout ;
; |part4|oDATA[3] ; |part4|SRAM_DQ[3]~output ; padio ;
; |part4|oDATA[4] ; |part4|oDATA[4] ; combout ;
; |part4|oDATA[4] ; |part4|SRAM_DQ[4]~output ; padio ;
; |part4|oDATA[5] ; |part4|oDATA[5] ; combout ;
; |part4|oDATA[5] ; |part4|SRAM_DQ[5]~output ; padio ;
; |part4|oDATA[6] ; |part4|oDATA[6] ; combout ;
; |part4|oDATA[6] ; |part4|SRAM_DQ[6]~output ; padio ;
; |part4|oDATA[7] ; |part4|oDATA[7] ; combout ;
; |part4|oDATA[7] ; |part4|SRAM_DQ[7]~output ; padio ;
; |part4|SRAM_DQ[8]~output ; |part4|SRAM_DQ[8]~output ; padio ;
; |part4|SRAM_DQ[9]~output ; |part4|SRAM_DQ[9]~output ; padio ;
; |part4|SRAM_DQ[10]~output ; |part4|SRAM_DQ[10]~output ; padio ;
; |part4|SRAM_DQ[11]~output ; |part4|SRAM_DQ[11]~output ; padio ;
; |part4|SRAM_DQ[12]~output ; |part4|SRAM_DQ[12]~output ; padio ;
; |part4|SRAM_DQ[13]~output ; |part4|SRAM_DQ[13]~output ; padio ;
; |part4|SRAM_DQ[14]~output ; |part4|SRAM_DQ[14]~output ; padio ;
; |part4|SRAM_DQ[15]~output ; |part4|SRAM_DQ[15]~output ; padio ;
; |part4|DATA[2]~feeder ; |part4|DATA[2]~feeder ; combout ;
; |part4|DATA[4]~feeder ; |part4|DATA[4]~feeder ; combout ;
; |part4|ADDR[0]~feeder ; |part4|ADDR[0]~feeder ; combout ;
; |part4|ADDR[1]~feeder ; |part4|ADDR[1]~feeder ; combout ;
; |part4|ADDR[2]~feeder ; |part4|ADDR[2]~feeder ; combout ;
; |part4|ADDR[3]~feeder ; |part4|ADDR[3]~feeder ; combout ;
; |part4|OE_N~feeder ; |part4|OE_N~feeder ; combout ;
+-------------------------------+-------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Wed Apr 18 22:29:25 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off part4 -c part4
Warning: Ignored node in vector source file. Can't find corresponding node name "WE_N" in design.
Warning: Can't find signal in vector source file for input pin "|part4|SW[8]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[9]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[10]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[16]"
Warning: Can't find signal in vector source file for input pin "|part4|KEY[1]"
Warning: Can't find signal in vector source file for input pin "|part4|KEY[2]"
Warning: Can't find signal in vector source file for input pin "|part4|KEY[3]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[0]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[1]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[2]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[3]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[4]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[5]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[6]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[7]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[11]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[12]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[13]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[14]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[15]"
Warning: Can't find signal in vector source file for input pin "|part4|SW[17]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[0]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[1]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[2]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[3]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[4]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[5]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[6]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[7]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[8]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[9]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[10]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[11]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[12]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[13]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[14]"
Warning: Can't find signal in vector source file for input pin "|part4|SRAM_DQ[15]"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 0.55 %
Info: Number of transitions in simulation is 236
Info: Quartus II Simulator was successful. 0 errors, 38 warnings
Info: Processing ended: Wed Apr 18 22:29:26 2007
Info: Elapsed time: 00:00:02
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