part4.v

基于FPGA的CPU设计 VHDL 编写

module	part4		(
						SW,KEY,LEDG,
						HEX0,HEX1,HEX2,
						HEX3,HEX4,HEX5,
						HEX6,HEX7,
						//	SRAM
						SRAM_DQ,
						SRAM_ADDR,
						SRAM_UB_N,
						SRAM_LB_N,
						SRAM_WE_N,
						SRAM_CE_N,
						SRAM_OE_N
						);

input	[17:0]	SW;
input	[3:0]	KEY;
output	[7:0]	LEDG;
output	[6:0]	HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
//	Host Side
wire	[15:0]	iDATA;
wire	[15:0]	oDATA;
wire	[17:0]	iADDR;
wire			iWE_N,iOE_N;
wire			clock;
//	SRAM Side
inout	[15:0]	SRAM_DQ;
output	[17:0]	SRAM_ADDR;
output			SRAM_UB_N,
				SRAM_LB_N,
				SRAM_WE_N,
				SRAM_CE_N,
				SRAM_OE_N;

reg		[7:0]	DATA;
reg		[4:0]	ADDR;
reg				WE_N;
reg				OE_N;

assign	iDATA		=	SW[7:0];
assign	iADDR		=	SW[15:11];
assign	clock		=	KEY[0];
assign	iWE_N		=	SW[17];

assign	SRAM_DQ 	=	SRAM_WE_N ? 16'hzzzz : DATA;
assign	oDATA		=	SRAM_DQ;
assign	SRAM_ADDR	=	ADDR;
assign	SRAM_WE_N	=	WE_N;
assign	SRAM_OE_N	=	OE_N;
assign	SRAM_CE_N	=	0;
assign	SRAM_UB_N	=	0;
assign	SRAM_LB_N	=	0;

always@(posedge clock)
begin
	if(iWE_N)
	begin
		WE_N	<=	0;
		OE_N	<=	1;
	end
	else
	begin
		WE_N	<=	1;
		OE_N	<=	0;
	end
	ADDR	<=	iADDR;
	DATA	<=	iDATA;
end

SEG7_LUT u1(.oSEG(HEX6),.iDIG(SW[14:11]));
SEG7_LUT u2(.oSEG(HEX7),.iDIG(SW[15]));
SEG7_LUT u3(.oSEG(HEX5),.iDIG(SW[7:4]));
SEG7_LUT u4(.oSEG(HEX4),.iDIG(SW[3:0]));
SEG7_LUT u5(.oSEG(HEX1),.iDIG(oDATA[7:4]));
SEG7_LUT u6(.oSEG(HEX0),.iDIG(oDATA[3:0]));


endmodule