part3.map.qmsg

来自「基于FPGA的CPU设计 VHDL 编写」· QMSG 代码 · 共 40 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 07 17:28:04 2007 " "Info: Processing started: Tue Aug 07 17:28:04 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part3 -c part3 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part3 -c part3" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_single.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram_single.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_single " "Info: Found entity 1: ram_single" {  } { { "ram_single.v" "" { Text "F:/altera/exercise/lab8/part3/ram_single.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "part3.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file part3.v" { { "Info" "ISGN_ENTITY_NAME" "1 part3 " "Info: Found entity 1: part3" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part3 " "Info: Elaborating entity \"part3\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[7\] part3.v(5) " "Warning (10034): Output port \"LEDG\[7\]\" at part3.v(5) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 5 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[6\] part3.v(5) " "Warning (10034): Output port \"LEDG\[6\]\" at part3.v(5) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 5 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[5\] part3.v(5) " "Warning (10034): Output port \"LEDG\[5\]\" at part3.v(5) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 5 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[4\] part3.v(5) " "Warning (10034): Output port \"LEDG\[4\]\" at part3.v(5) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 5 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[3\] part3.v(5) " "Warning (10034): Output port \"LEDG\[3\]\" at part3.v(5) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 5 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[2\] part3.v(5) " "Warning (10034): Output port \"LEDG\[2\]\" at part3.v(5) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 5 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDG\[1\] part3.v(5) " "Warning (10034): Output port \"LEDG\[1\]\" at part3.v(5) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 5 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "HEX2\[6\] part3.v(6) " "Warning (10034): Output port \"HEX2\[6\]\" at part3.v(6) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "HEX2\[5\] part3.v(6) " "Warning (10034): Output port \"HEX2\[5\]\" at part3.v(6) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "HEX2\[4\] part3.v(6) " "Warning (10034): Output port \"HEX2\[4\]\" at part3.v(6) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "HEX2\[3\] part3.v(6) " "Warning (10034): Output port \"HEX2\[3\]\" at part3.v(6) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "HEX2\[2\] part3.v(6) " "Warning (10034): Output port \"HEX2\[2\]\" at part3.v(6) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "HEX2\[1\] part3.v(6) " "Warning (10034): Output port \"HEX2\[1\]\" at part3.v(6) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "HEX2\[0\] part3.v(6) " "Warning (10034): Output port \"HEX2\[0\]\" at part3.v(6) has no driver" {  } { { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}