part3.tan.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "ITDB_TH_RESULT" "ram_single:u0\|altsyncram:mem_array_rtl_0\|altsyncram_n861:auto_generated\|ram_block1a0~porta_address_reg1 SW\[12\] KEY\[0\] 1.519 ns memory " "Info: th for memory \"ram_single:u0\|altsyncram:mem_array_rtl_0\|altsyncram_n861:auto_generated\|ram_block1a0~porta_address_reg1\" (data pin = \"SW\[12\]\", clock pin = \"KEY\[0\]\") is 1.519 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY\[0\] destination 3.973 ns + Longest memory " "Info: + Longest clock path from clock \"KEY\[0\]\" to destination memory is 3.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns KEY\[0\] 1 CLK PIN_G26 22 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 22; CLK Node = 'KEY\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.450 ns) + CELL(0.661 ns) 3.973 ns ram_single:u0\|altsyncram:mem_array_rtl_0\|altsyncram_n861:auto_generated\|ram_block1a0~porta_address_reg1 2 MEM M4K_X26_Y14 8 " "Info: 2: + IC(2.450 ns) + CELL(0.661 ns) = 3.973 ns; Loc. = M4K_X26_Y14; Fanout = 8; MEM Node = 'ram_single:u0\|altsyncram:mem_array_rtl_0\|altsyncram_n861:auto_generated\|ram_block1a0~porta_address_reg1'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { KEY[0] ram_single:u0|altsyncram:mem_array_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "db/altsyncram_n861.tdf" "" { Text "F:/altera/exercise/lab8/part3/db/altsyncram_n861.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.523 ns ( 38.33 % ) " "Info: Total cell delay = 1.523 ns ( 38.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.450 ns ( 61.67 % ) " "Info: Total interconnect delay = 2.450 ns ( 61.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.973 ns" { KEY[0] ram_single:u0|altsyncram:mem_array_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.973 ns" { KEY[0] KEY[0]~combout ram_single:u0|altsyncram:mem_array_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 2.450ns } { 0.000ns 0.862ns 0.661ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.234 ns + " "Info: + Micro hold delay of destination is 0.234 ns" {  } { { "db/altsyncram_n861.tdf" "" { Text "F:/altera/exercise/lab8/part3/db/altsyncram_n861.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.688 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 2.688 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns SW\[12\] 1 PIN PIN_P2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 8; PIN Node = 'SW\[12\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW[12] } "NODE_NAME" } } { "part3.v" "" { Text "F:/altera/exercise/lab8/part3/part3.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.547 ns) + CELL(0.142 ns) 2.688 ns ram_single:u0\|altsyncram:mem_array_rtl_0\|altsyncram_n861:auto_generated\|ram_block1a0~porta_address_reg1 2 MEM M4K_X26_Y14 8 " "Info: 2: + IC(1.547 ns) + CELL(0.142 ns) = 2.688 ns; Loc. = M4K_X26_Y14; Fanout = 8; MEM Node = 'ram_single:u0\|altsyncram:mem_array_rtl_0\|altsyncram_n861:auto_generated\|ram_block1a0~porta_address_reg1'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.689 ns" { SW[12] ram_single:u0|altsyncram:mem_array_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "db/altsyncram_n861.tdf" "" { Text "F:/altera/exercise/lab8/part3/db/altsyncram_n861.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.141 ns ( 42.45 % ) " "Info: Total cell delay = 1.141 ns ( 42.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.547 ns ( 57.55 % ) " "Info: Total interconnect delay = 1.547 ns ( 57.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.688 ns" { SW[12] ram_single:u0|altsyncram:mem_array_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.688 ns" { SW[12] SW[12]~combout ram_single:u0|altsyncram:mem_array_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 1.547ns } { 0.000ns 0.999ns 0.142ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.973 ns" { KEY[0] ram_single:u0|altsyncram:mem_array_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.973 ns" { KEY[0] KEY[0]~combout ram_single:u0|altsyncram:mem_array_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 2.450ns } { 0.000ns 0.862ns 0.661ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.688 ns" { SW[12] ram_single:u0|altsyncram:mem_array_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.688 ns" { SW[12] SW[12]~combout ram_single:u0|altsyncram:mem_array_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_address_reg1 } { 0.000ns 0.000ns 1.547ns } { 0.000ns 0.999ns 0.142ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 07 17:29:34 2007 " "Info: Processing ended: Tue Aug 07 17:29:34 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}