part3.map.summary

来自「基于FPGA的CPU设计 VHDL 编写」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Tue Aug 07 17:28:10 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : part3
Top-level Entity Name : part3
Family : Cyclone II
Total logic elements : 35
Total registers : 0
Total pins : 86
Total virtual pins : 0
Total memory bits : 256
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0