ram_single.v

来自「基于FPGA的CPU设计 VHDL 编写」· Verilog 代码 · 共 20 行

module ram_single(addr,data,we,clock,q);

input	[4:0]	addr;
input	[7:0]	data;
input			we,clock;
output	[7:0]	q;

reg		[4:0]	read_addr;
reg		[7:0]	mem_array[31:0];

assign	q	=	mem_array[read_addr];

always@(posedge clock)
begin
	if(we)
		mem_array[addr]	<=	data;
	read_addr		<=	addr;
end

endmodule