part2.map.rpt

来自「基于FPGA的CPU设计 VHDL 编写」· RPT 代码 · 共 361 行 · 第 1/3 页

; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                         ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                         ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                         ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                         ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                         ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                         ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                         ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                         ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                         ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                         ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                         ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                         ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                         ;
; RAM_BLOCK_TYPE                     ; M4K             ; Untyped                         ;
; BYTE_SIZE                          ; 8               ; Untyped                         ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                         ;
; INIT_FILE                          ; UNUSED          ; Untyped                         ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                         ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                         ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                         ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                         ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                         ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                         ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                         ;
; CBXI_PARAMETER                     ; altsyncram_s8h1 ; Untyped                         ;
+------------------------------------+-----------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Aug 07 15:49:31 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part2 -c part2
Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v
    Info: Found entity 1: SEG7_LUT
Info: Found 1 design units, including 1 entities, in source file part2.v
    Info: Found entity 1: part2
Info: Elaborating entity "part2" for the top level hierarchy
Warning (10034): Output port "LEDG[7]" at part2.v(5) has no driver
Warning (10034): Output port "LEDG[6]" at part2.v(5) has no driver
Warning (10034): Output port "LEDG[5]" at part2.v(5) has no driver
Warning (10034): Output port "LEDG[4]" at part2.v(5) has no driver
Warning (10034): Output port "LEDG[3]" at part2.v(5) has no driver
Warning (10034): Output port "LEDG[2]" at part2.v(5) has no driver
Warning (10034): Output port "LEDG[1]" at part2.v(5) has no driver
Warning (10034): Output port "HEX2[6]" at part2.v(6) has no driver
Warning (10034): Output port "HEX2[5]" at part2.v(6) has no driver
Warning (10034): Output port "HEX2[4]" at part2.v(6) has no driver
Warning (10034): Output port "HEX2[3]" at part2.v(6) has no driver
Warning (10034): Output port "HEX2[2]" at part2.v(6) has no driver
Warning (10034): Output port "HEX2[1]" at part2.v(6) has no driver
Warning (10034): Output port "HEX2[0]" at part2.v(6) has no driver
Warning (10034): Output port "HEX3[6]" at part2.v(6) has no driver
Warning (10034): Output port "HEX3[5]" at part2.v(6) has no driver
Warning (10034): Output port "HEX3[4]" at part2.v(6) has no driver
Warning (10034): Output port "HEX3[3]" at part2.v(6) has no driver
Warning (10034): Output port "HEX3[2]" at part2.v(6) has no driver
Warning (10034): Output port "HEX3[1]" at part2.v(6) has no driver
Warning (10034): Output port "HEX3[0]" at part2.v(6) has no driver
Warning: Using design file ramlpm.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ramlpm
Info: Elaborating entity "ramlpm" for hierarchy "ramlpm:u0"
Info: Found 1 design units, including 1 entities, in source file ../../../quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "ramlpm:u0|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "ramlpm:u0|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_s8h1.tdf
    Info: Found entity 1: altsyncram_s8h1
Info: Elaborating entity "altsyncram_s8h1" for hierarchy "ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated"
Info: Elaborating entity "SEG7_LUT" for hierarchy "SEG7_LUT:u1"
Warning: Port "iDIG" on the entity instantiation of "u2" is connected to a signal of width 1. The formal width of the signal in the module is 4.  Extra bits will be driven by GND.
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "LEDG[1]" stuck at GND
    Warning: Pin "LEDG[2]" stuck at GND
    Warning: Pin "LEDG[3]" stuck at GND
    Warning: Pin "LEDG[4]" stuck at GND
    Warning: Pin "LEDG[5]" stuck at GND
    Warning: Pin "LEDG[6]" stuck at GND
    Warning: Pin "LEDG[7]" stuck at GND
    Warning: Pin "HEX2[0]" stuck at GND
    Warning: Pin "HEX2[1]" stuck at GND
    Warning: Pin "HEX2[2]" stuck at GND
    Warning: Pin "HEX2[3]" stuck at GND
    Warning: Pin "HEX2[4]" stuck at GND
    Warning: Pin "HEX2[5]" stuck at GND
    Warning: Pin "HEX2[6]" stuck at GND
    Warning: Pin "HEX3[0]" stuck at GND
    Warning: Pin "HEX3[1]" stuck at GND
    Warning: Pin "HEX3[2]" stuck at GND
    Warning: Pin "HEX3[3]" stuck at GND
    Warning: Pin "HEX3[4]" stuck at GND
    Warning: Pin "HEX3[5]" stuck at GND
    Warning: Pin "HEX3[6]" stuck at GND
    Warning: Pin "HEX7[1]" stuck at GND
    Warning: Pin "HEX7[2]" stuck at GND
    Warning: Pin "HEX7[6]" stuck at VCC
Warning: Design contains 7 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "SW[8]"
    Warning: No output dependent on input pin "SW[9]"
    Warning: No output dependent on input pin "SW[10]"
    Warning: No output dependent on input pin "SW[16]"
    Warning: No output dependent on input pin "KEY[1]"
    Warning: No output dependent on input pin "KEY[2]"
    Warning: No output dependent on input pin "KEY[3]"
Info: Implemented 129 device resources after synthesis - the final resource count might be different
    Info: Implemented 22 input pins
    Info: Implemented 64 output pins
    Info: Implemented 35 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 56 warnings
    Info: Processing ended: Tue Aug 07 15:49:35 2007
    Info: Elapsed time: 00:00:04