part2.hier_info

基于FPGA的CPU设计 VHDL 编写

|part2
SW[0] => SW[0]~13.IN2
SW[1] => SW[1]~12.IN2
SW[2] => SW[2]~11.IN2
SW[3] => SW[3]~10.IN2
SW[4] => SW[4]~9.IN2
SW[5] => SW[5]~8.IN2
SW[6] => SW[6]~7.IN2
SW[7] => SW[7]~6.IN2
SW[8] => ~NO_FANOUT~
SW[9] => ~NO_FANOUT~
SW[10] => ~NO_FANOUT~
SW[11] => SW[11]~5.IN2
SW[12] => SW[12]~4.IN2
SW[13] => SW[13]~3.IN2
SW[14] => SW[14]~2.IN2
SW[15] => SW[15]~1.IN2
SW[16] => ~NO_FANOUT~
SW[17] => SW[17]~0.IN1
KEY[0] => KEY[0]~0.IN1
KEY[1] => ~NO_FANOUT~
KEY[2] => ~NO_FANOUT~
KEY[3] => ~NO_FANOUT~
LEDG[0] <= SW[17]~0.DB_MAX_OUTPUT_PORT_TYPE
LEDG[1] <= <GND>
LEDG[2] <= <GND>
LEDG[3] <= <GND>
LEDG[4] <= <GND>
LEDG[5] <= <GND>
LEDG[6] <= <GND>
LEDG[7] <= <GND>
HEX0[0] <= SEG7_LUT:u6.oSEG
HEX0[1] <= SEG7_LUT:u6.oSEG
HEX0[2] <= SEG7_LUT:u6.oSEG
HEX0[3] <= SEG7_LUT:u6.oSEG
HEX0[4] <= SEG7_LUT:u6.oSEG
HEX0[5] <= SEG7_LUT:u6.oSEG
HEX0[6] <= SEG7_LUT:u6.oSEG
HEX1[0] <= SEG7_LUT:u5.oSEG
HEX1[1] <= SEG7_LUT:u5.oSEG
HEX1[2] <= SEG7_LUT:u5.oSEG
HEX1[3] <= SEG7_LUT:u5.oSEG
HEX1[4] <= SEG7_LUT:u5.oSEG
HEX1[5] <= SEG7_LUT:u5.oSEG
HEX1[6] <= SEG7_LUT:u5.oSEG
HEX2[0] <= <GND>
HEX2[1] <= <GND>
HEX2[2] <= <GND>
HEX2[3] <= <GND>
HEX2[4] <= <GND>
HEX2[5] <= <GND>
HEX2[6] <= <GND>
HEX3[0] <= <GND>
HEX3[1] <= <GND>
HEX3[2] <= <GND>
HEX3[3] <= <GND>
HEX3[4] <= <GND>
HEX3[5] <= <GND>
HEX3[6] <= <GND>
HEX4[0] <= SEG7_LUT:u4.oSEG
HEX4[1] <= SEG7_LUT:u4.oSEG
HEX4[2] <= SEG7_LUT:u4.oSEG
HEX4[3] <= SEG7_LUT:u4.oSEG
HEX4[4] <= SEG7_LUT:u4.oSEG
HEX4[5] <= SEG7_LUT:u4.oSEG
HEX4[6] <= SEG7_LUT:u4.oSEG
HEX5[0] <= SEG7_LUT:u3.oSEG
HEX5[1] <= SEG7_LUT:u3.oSEG
HEX5[2] <= SEG7_LUT:u3.oSEG
HEX5[3] <= SEG7_LUT:u3.oSEG
HEX5[4] <= SEG7_LUT:u3.oSEG
HEX5[5] <= SEG7_LUT:u3.oSEG
HEX5[6] <= SEG7_LUT:u3.oSEG
HEX6[0] <= SEG7_LUT:u1.oSEG
HEX6[1] <= SEG7_LUT:u1.oSEG
HEX6[2] <= SEG7_LUT:u1.oSEG
HEX6[3] <= SEG7_LUT:u1.oSEG
HEX6[4] <= SEG7_LUT:u1.oSEG
HEX6[5] <= SEG7_LUT:u1.oSEG
HEX6[6] <= SEG7_LUT:u1.oSEG
HEX7[0] <= SEG7_LUT:u2.oSEG
HEX7[1] <= SEG7_LUT:u2.oSEG
HEX7[2] <= SEG7_LUT:u2.oSEG
HEX7[3] <= SEG7_LUT:u2.oSEG
HEX7[4] <= SEG7_LUT:u2.oSEG
HEX7[5] <= SEG7_LUT:u2.oSEG
HEX7[6] <= SEG7_LUT:u2.oSEG


|part2|ramlpm:u0
address[0] => address[0]~4.IN1
address[1] => address[1]~3.IN1
address[2] => address[2]~2.IN1
address[3] => address[3]~1.IN1
address[4] => address[4]~0.IN1
clock => clock~0.IN1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
wren => wren~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|part2|ramlpm:u0|altsyncram:altsyncram_component
wren_a => altsyncram_s8h1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_s8h1:auto_generated.data_a[0]
data_a[1] => altsyncram_s8h1:auto_generated.data_a[1]
data_a[2] => altsyncram_s8h1:auto_generated.data_a[2]
data_a[3] => altsyncram_s8h1:auto_generated.data_a[3]
data_a[4] => altsyncram_s8h1:auto_generated.data_a[4]
data_a[5] => altsyncram_s8h1:auto_generated.data_a[5]
data_a[6] => altsyncram_s8h1:auto_generated.data_a[6]
data_a[7] => altsyncram_s8h1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_s8h1:auto_generated.address_a[0]
address_a[1] => altsyncram_s8h1:auto_generated.address_a[1]
address_a[2] => altsyncram_s8h1:auto_generated.address_a[2]
address_a[3] => altsyncram_s8h1:auto_generated.address_a[3]
address_a[4] => altsyncram_s8h1:auto_generated.address_a[4]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_s8h1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_s8h1:auto_generated.q_a[0]
q_a[1] <= altsyncram_s8h1:auto_generated.q_a[1]
q_a[2] <= altsyncram_s8h1:auto_generated.q_a[2]
q_a[3] <= altsyncram_s8h1:auto_generated.q_a[3]
q_a[4] <= altsyncram_s8h1:auto_generated.q_a[4]
q_a[5] <= altsyncram_s8h1:auto_generated.q_a[5]
q_a[6] <= altsyncram_s8h1:auto_generated.q_a[6]
q_a[7] <= altsyncram_s8h1:auto_generated.q_a[7]
q_b[0] <= <GND>


|part2|ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE


|part2|SEG7_LUT:u1
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|part2|SEG7_LUT:u2
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|part2|SEG7_LUT:u3
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|part2|SEG7_LUT:u4
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|part2|SEG7_LUT:u5
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|part2|SEG7_LUT:u6
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0