part2.tan.qmsg

基于FPGA的CPU设计 VHDL 编写

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "KEY\[0\] memory memory ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_datain_reg0 ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_memory_reg0 200.0 MHz Internal " "Info: Clock \"KEY\[0\]\" Internal fmax is restricted to 200.0 MHz between source memory \"ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_datain_reg0\" and destination memory \"ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_memory_reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.645 ns + Longest memory memory " "Info: + Longest memory to memory delay is 2.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_datain_reg0 1 MEM M4K_X26_Y14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X26_Y14; Fanout = 1; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.645 ns) 2.645 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_memory_reg0 2 MEM M4K_X26_Y14 0 " "Info: 2: + IC(0.000 ns) + CELL(2.645 ns) = 2.645 ns; Loc. = M4K_X26_Y14; Fanout = 0; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_memory_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.645 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.645 ns ( 100.00 % ) " "Info: Total cell delay = 2.645 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.645 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.645 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 2.645ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.025 ns - Smallest " "Info: - Smallest clock skew is -0.025 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY\[0\] destination 3.947 ns + Shortest memory " "Info: + Shortest clock path from clock \"KEY\[0\]\" to destination memory is 3.947 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns KEY\[0\] 1 CLK PIN_G26 22 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 22; CLK Node = 'KEY\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "part2.v" "" { Text "F:/altera/exercise/lab8/part2/part2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.450 ns) + CELL(0.635 ns) 3.947 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_memory_reg0 2 MEM M4K_X26_Y14 0 " "Info: 2: + IC(2.450 ns) + CELL(0.635 ns) = 3.947 ns; Loc. = M4K_X26_Y14; Fanout = 0; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_memory_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.085 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.497 ns ( 37.93 % ) " "Info: Total cell delay = 1.497 ns ( 37.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.450 ns ( 62.07 % ) " "Info: Total interconnect delay = 2.450 ns ( 62.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.947 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.947 ns" { KEY[0] KEY[0]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns 2.450ns } { 0.000ns 0.862ns 0.635ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY\[0\] source 3.972 ns - Longest memory " "Info: - Longest clock path from clock \"KEY\[0\]\" to source memory is 3.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns KEY\[0\] 1 CLK PIN_G26 22 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 22; CLK Node = 'KEY\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "part2.v" "" { Text "F:/altera/exercise/lab8/part2/part2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.450 ns) + CELL(0.660 ns) 3.972 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_datain_reg0 2 MEM M4K_X26_Y14 1 " "Info: 2: + IC(2.450 ns) + CELL(0.660 ns) = 3.972 ns; Loc. = M4K_X26_Y14; Fanout = 1; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.110 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.522 ns ( 38.32 % ) " "Info: Total cell delay = 1.522 ns ( 38.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.450 ns ( 61.68 % ) " "Info: Total interconnect delay = 2.450 ns ( 61.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.972 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.972 ns" { KEY[0] KEY[0]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 2.450ns } { 0.000ns 0.862ns 0.660ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.947 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.947 ns" { KEY[0] KEY[0]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns 2.450ns } { 0.000ns 0.862ns 0.635ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.972 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.972 ns" { KEY[0] KEY[0]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 2.450ns } { 0.000ns 0.862ns 0.660ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.645 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.645 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 2.645ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.947 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.947 ns" { KEY[0] KEY[0]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns 2.450ns } { 0.000ns 0.862ns 0.635ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.972 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.972 ns" { KEY[0] KEY[0]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 2.450ns } { 0.000ns 0.862ns 0.660ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0 } {  } {  } } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_address_reg4 SW\[15\] KEY\[0\] 2.965 ns memory " "Info: tsu for memory \"ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_address_reg4\" (data pin = \"SW\[15\]\", clock pin = \"KEY\[0\]\") is 2.965 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.903 ns + Longest pin memory " "Info: + Longest pin to memory delay is 6.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns SW\[15\] 1 PIN PIN_U4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_U4; Fanout = 5; PIN Node = 'SW\[15\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW[15] } "NODE_NAME" } } { "part2.v" "" { Text "F:/altera/exercise/lab8/part2/part2.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.929 ns) + CELL(0.142 ns) 6.903 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_address_reg4 2 MEM M4K_X26_Y14 8 " "Info: 2: + IC(5.929 ns) + CELL(0.142 ns) = 6.903 ns; Loc. = M4K_X26_Y14; Fanout = 8; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_address_reg4'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.071 ns" { SW[15] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.974 ns ( 14.11 % ) " "Info: Total cell delay = 0.974 ns ( 14.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.929 ns ( 85.89 % ) " "Info: Total interconnect delay = 5.929 ns ( 85.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.903 ns" { SW[15] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.903 ns" { SW[15] SW[15]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 5.929ns } { 0.000ns 0.832ns 0.142ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY\[0\] destination 3.973 ns - Shortest memory " "Info: - Shortest clock path from clock \"KEY\[0\]\" to destination memory is 3.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns KEY\[0\] 1 CLK PIN_G26 22 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 22; CLK Node = 'KEY\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "part2.v" "" { Text "F:/altera/exercise/lab8/part2/part2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.450 ns) + CELL(0.661 ns) 3.973 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_address_reg4 2 MEM M4K_X26_Y14 8 " "Info: 2: + IC(2.450 ns) + CELL(0.661 ns) = 3.973 ns; Loc. = M4K_X26_Y14; Fanout = 8; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_address_reg4'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.523 ns ( 38.33 % ) " "Info: Total cell delay = 1.523 ns ( 38.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.450 ns ( 61.67 % ) " "Info: Total interconnect delay = 2.450 ns ( 61.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.973 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.973 ns" { KEY[0] KEY[0]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 2.450ns } { 0.000ns 0.862ns 0.661ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.903 ns" { SW[15] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.903 ns" { SW[15] SW[15]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 5.929ns } { 0.000ns 0.832ns 0.142ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.973 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.973 ns" { KEY[0] KEY[0]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4 } { 0.000ns 0.000ns 2.450ns } { 0.000ns 0.862ns 0.661ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "KEY\[0\] HEX1\[1\] ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg 14.731 ns memory " "Info: tco from clock \"KEY\[0\]\" to destination pin \"HEX1\[1\]\" through memory \"ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg\" is 14.731 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY\[0\] source 3.973 ns + Longest memory " "Info: + Longest clock path from clock \"KEY\[0\]\" to source memory is 3.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns KEY\[0\] 1 CLK PIN_G26 22 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 22; CLK Node = 'KEY\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "part2.v" "" { Text "F:/altera/exercise/lab8/part2/part2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.450 ns) + CELL(0.661 ns) 3.973 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg 2 MEM M4K_X26_Y14 8 " "Info: 2: + IC(2.450 ns) + CELL(0.661 ns) = 3.973 ns; Loc. = M4K_X26_Y14; Fanout = 8; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.523 ns ( 38.33 % ) " "Info: Total cell delay = 1.523 ns ( 38.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.450 ns ( 61.67 % ) " "Info: Total interconnect delay = 2.450 ns ( 61.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.973 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.973 ns" { KEY[0] KEY[0]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 2.450ns } { 0.000ns 0.862ns 0.661ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.549 ns + Longest memory pin " "Info: + Longest memory to pin delay is 10.549 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg 1 MEM M4K_X26_Y14 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X26_Y14; Fanout = 8; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 45 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.993 ns) 2.993 ns ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|q_a\[6\] 2 MEM M4K_X26_Y14 7 " "Info: 2: + IC(0.000 ns) + CELL(2.993 ns) = 2.993 ns; Loc. = M4K_X26_Y14; Fanout = 7; MEM Node = 'ramlpm:u0\|altsyncram:altsyncram_component\|altsyncram_s8h1:auto_generated\|q_a\[6\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.993 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[6] } "NODE_NAME" } } { "db/altsyncram_s8h1.tdf" "" { Text "F:/altera/exercise/lab8/part2/db/altsyncram_s8h1.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.741 ns) + CELL(0.275 ns) 7.009 ns SEG7_LUT:u5\|WideOr5~4 3 COMB LCCOMB_X64_Y5_N10 1 " "Info: 3: + IC(3.741 ns) + CELL(0.275 ns) = 7.009 ns; Loc. = LCCOMB_X64_Y5_N10; Fanout = 1; COMB Node = 'SEG7_LUT:u5\|WideOr5~4'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.016 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[6] SEG7_LUT:u5|WideOr5~4 } "NODE_NAME" } } { "SEG7_LUT.v" "" { Text "F:/altera/exercise/lab8/part2/SEG7_LUT.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(2.789 ns) 10.549 ns HEX1\[1\] 4 PIN PIN_V21 0 " "Info: 4: + IC(0.751 ns) + CELL(2.789 ns) = 10.549 ns; Loc. = PIN_V21; Fanout = 0; PIN Node = 'HEX1\[1\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.540 ns" { SEG7_LUT:u5|WideOr5~4 HEX1[1] } "NODE_NAME" } } { "part2.v" "" { Text "F:/altera/exercise/lab8/part2/part2.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.057 ns ( 57.42 % ) " "Info: Total cell delay = 6.057 ns ( 57.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.492 ns ( 42.58 % ) " "Info: Total interconnect delay = 4.492 ns ( 42.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.549 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[6] SEG7_LUT:u5|WideOr5~4 HEX1[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "10.549 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[6] SEG7_LUT:u5|WideOr5~4 HEX1[1] } { 0.000ns 0.000ns 3.741ns 0.751ns } { 0.000ns 2.993ns 0.275ns 2.789ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.973 ns" { KEY[0] ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.973 ns" { KEY[0] KEY[0]~combout ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg } { 0.000ns 0.000ns 2.450ns } { 0.000ns 0.862ns 0.661ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.549 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[6] SEG7_LUT:u5|WideOr5~4 HEX1[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "10.549 ns" { ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[6] SEG7_LUT:u5|WideOr5~4 HEX1[1] } { 0.000ns 0.000ns 3.741ns 0.751ns } { 0.000ns 2.993ns 0.275ns 2.789ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SW\[17\] LEDG\[0\] 10.234 ns Longest " "Info: Longest tpd from source pin \"SW\[17\]\" to destination pin \"LEDG\[0\]\" is 10.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns SW\[17\] 1 PIN PIN_V2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 2; PIN Node = 'SW\[17\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SW[17] } "NODE_NAME" } } { "part2.v" "" { Text "F:/altera/exercise/lab8/part2/part2.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.574 ns) + CELL(2.808 ns) 10.234 ns LEDG\[0\] 2 PIN PIN_AE22 0 " "Info: 2: + IC(6.574 ns) + CELL(2.808 ns) = 10.234 ns; Loc. = PIN_AE22; Fanout = 0; PIN Node = 'LEDG\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.382 ns" { SW[17] LEDG[0] } "NODE_NAME" } } { "part2.v" "" { Text "F:/altera/exercise/lab8/part2/part2.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.660 ns ( 35.76 % ) " "Info: Total cell delay = 3.660 ns ( 35.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.574 ns ( 64.24 % ) " "Info: Total interconnect delay = 6.574 ns ( 64.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.234 ns" { SW[17] LEDG[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "10.234 ns" { SW[17] SW[17]~combout LEDG[0] } { 0.000ns 0.000ns 6.574ns } { 0.000ns 0.852ns 2.808ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}