part2.v

基于FPGA的CPU设计 VHDL 编写

module part2(SW,KEY,LEDG,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7);

input	[17:0]	SW;
input	[3:0]	KEY;
output	[7:0]	LEDG;
output	[6:0]	HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;

wire	[7:0]	Q;

assign	LEDG[0]	=	SW[17];

ramlpm u0(
			.address(SW[15:11]),
			.clock(KEY[0]),
			.data(SW[7:0]),
			.wren(SW[17]),
			.q(Q)
			);
SEG7_LUT u1(.oSEG(HEX6),.iDIG(SW[14:11]));
SEG7_LUT u2(.oSEG(HEX7),.iDIG(SW[15]));
SEG7_LUT u3(.oSEG(HEX5),.iDIG(SW[7:4]));
SEG7_LUT u4(.oSEG(HEX4),.iDIG(SW[3:0]));
SEG7_LUT u5(.oSEG(HEX1),.iDIG(Q[7:4]));
SEG7_LUT u6(.oSEG(HEX0),.iDIG(Q[3:0]));


endmodule