part2.tan.rpt

基于FPGA的CPU设计 VHDL 编写

; N/A   ; None              ; 5.051 ns        ; SW[11] ; HEX6[0] ;
+-------+-------------------+-----------------+--------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                                     ;
+---------------+-------------+-----------+--------+----------------------------------------------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To                                                                                                       ; To Clock ;
+---------------+-------------+-----------+--------+----------------------------------------------------------------------------------------------------------+----------+
; N/A           ; None        ; 1.519 ns  ; SW[12] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg1 ; KEY[0]   ;
; N/A           ; None        ; 1.325 ns  ; SW[3]  ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg3  ; KEY[0]   ;
; N/A           ; None        ; 1.214 ns  ; SW[11] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg0 ; KEY[0]   ;
; N/A           ; None        ; 1.202 ns  ; SW[6]  ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg6  ; KEY[0]   ;
; N/A           ; None        ; 1.173 ns  ; SW[1]  ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg1  ; KEY[0]   ;
; N/A           ; None        ; 1.104 ns  ; SW[5]  ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg5  ; KEY[0]   ;
; N/A           ; None        ; 1.004 ns  ; SW[4]  ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg4  ; KEY[0]   ;
; N/A           ; None        ; 0.994 ns  ; SW[7]  ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg7  ; KEY[0]   ;
; N/A           ; None        ; 0.764 ns  ; SW[0]  ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0  ; KEY[0]   ;
; N/A           ; None        ; 0.377 ns  ; SW[2]  ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg2  ; KEY[0]   ;
; N/A           ; None        ; -2.454 ns ; SW[13] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg2 ; KEY[0]   ;
; N/A           ; None        ; -2.583 ns ; SW[14] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg3 ; KEY[0]   ;
; N/A           ; None        ; -2.656 ns ; SW[17] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg       ; KEY[0]   ;
; N/A           ; None        ; -2.696 ns ; SW[15] ; ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4 ; KEY[0]   ;
+---------------+-------------+-----------+--------+----------------------------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Aug 07 15:50:27 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part2 -c part2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "KEY[0]" is an undefined clock
Info: Clock "KEY[0]" Internal fmax is restricted to 200.0 MHz between source memory "ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0" and destination memory "ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest memory to memory delay is 2.645 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X26_Y14; Fanout = 1; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0'
            Info: 2: + IC(0.000 ns) + CELL(2.645 ns) = 2.645 ns; Loc. = M4K_X26_Y14; Fanout = 0; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0'
            Info: Total cell delay = 2.645 ns ( 100.00 % )
        Info: - Smallest clock skew is -0.025 ns
            Info: + Shortest clock path from clock "KEY[0]" to destination memory is 3.947 ns
                Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 22; CLK Node = 'KEY[0]'
                Info: 2: + IC(2.450 ns) + CELL(0.635 ns) = 3.947 ns; Loc. = M4K_X26_Y14; Fanout = 0; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_memory_reg0'
                Info: Total cell delay = 1.497 ns ( 37.93 % )
                Info: Total interconnect delay = 2.450 ns ( 62.07 % )
            Info: - Longest clock path from clock "KEY[0]" to source memory is 3.972 ns
                Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 22; CLK Node = 'KEY[0]'
                Info: 2: + IC(2.450 ns) + CELL(0.660 ns) = 3.972 ns; Loc. = M4K_X26_Y14; Fanout = 1; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_datain_reg0'
                Info: Total cell delay = 1.522 ns ( 38.32 % )
                Info: Total interconnect delay = 2.450 ns ( 61.68 % )
        Info: + Micro clock to output delay of source is 0.209 ns
        Info: + Micro setup delay of destination is 0.035 ns
Info: tsu for memory "ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4" (data pin = "SW[15]", clock pin = "KEY[0]") is 2.965 ns
    Info: + Longest pin to memory delay is 6.903 ns
        Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_U4; Fanout = 5; PIN Node = 'SW[15]'
        Info: 2: + IC(5.929 ns) + CELL(0.142 ns) = 6.903 ns; Loc. = M4K_X26_Y14; Fanout = 8; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4'
        Info: Total cell delay = 0.974 ns ( 14.11 % )
        Info: Total interconnect delay = 5.929 ns ( 85.89 % )
    Info: + Micro setup delay of destination is 0.035 ns
    Info: - Shortest clock path from clock "KEY[0]" to destination memory is 3.973 ns
        Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 22; CLK Node = 'KEY[0]'
        Info: 2: + IC(2.450 ns) + CELL(0.661 ns) = 3.973 ns; Loc. = M4K_X26_Y14; Fanout = 8; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg4'
        Info: Total cell delay = 1.523 ns ( 38.33 % )
        Info: Total interconnect delay = 2.450 ns ( 61.67 % )
Info: tco from clock "KEY[0]" to destination pin "HEX1[1]" through memory "ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg" is 14.731 ns
    Info: + Longest clock path from clock "KEY[0]" to source memory is 3.973 ns
        Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 22; CLK Node = 'KEY[0]'
        Info: 2: + IC(2.450 ns) + CELL(0.661 ns) = 3.973 ns; Loc. = M4K_X26_Y14; Fanout = 8; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg'
        Info: Total cell delay = 1.523 ns ( 38.33 % )
        Info: Total interconnect delay = 2.450 ns ( 61.67 % )
    Info: + Micro clock to output delay of source is 0.209 ns
    Info: + Longest memory to pin delay is 10.549 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X26_Y14; Fanout = 8; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_we_reg'
        Info: 2: + IC(0.000 ns) + CELL(2.993 ns) = 2.993 ns; Loc. = M4K_X26_Y14; Fanout = 7; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|q_a[6]'
        Info: 3: + IC(3.741 ns) + CELL(0.275 ns) = 7.009 ns; Loc. = LCCOMB_X64_Y5_N10; Fanout = 1; COMB Node = 'SEG7_LUT:u5|WideOr5~4'
        Info: 4: + IC(0.751 ns) + CELL(2.789 ns) = 10.549 ns; Loc. = PIN_V21; Fanout = 0; PIN Node = 'HEX1[1]'
        Info: Total cell delay = 6.057 ns ( 57.42 % )
        Info: Total interconnect delay = 4.492 ns ( 42.58 % )
Info: Longest tpd from source pin "SW[17]" to destination pin "LEDG[0]" is 10.234 ns
    Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 2; PIN Node = 'SW[17]'
    Info: 2: + IC(6.574 ns) + CELL(2.808 ns) = 10.234 ns; Loc. = PIN_AE22; Fanout = 0; PIN Node = 'LEDG[0]'
    Info: Total cell delay = 3.660 ns ( 35.76 % )
    Info: Total interconnect delay = 6.574 ns ( 64.24 % )
Info: th for memory "ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg1" (data pin = "SW[12]", clock pin = "KEY[0]") is 1.519 ns
    Info: + Longest clock path from clock "KEY[0]" to destination memory is 3.973 ns
        Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 22; CLK Node = 'KEY[0]'
        Info: 2: + IC(2.450 ns) + CELL(0.661 ns) = 3.973 ns; Loc. = M4K_X26_Y14; Fanout = 8; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg1'
        Info: Total cell delay = 1.523 ns ( 38.33 % )
        Info: Total interconnect delay = 2.450 ns ( 61.67 % )
    Info: + Micro hold delay of destination is 0.234 ns
    Info: - Shortest pin to memory delay is 2.688 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 8; PIN Node = 'SW[12]'
        Info: 2: + IC(1.547 ns) + CELL(0.142 ns) = 2.688 ns; Loc. = M4K_X26_Y14; Fanout = 8; MEM Node = 'ramlpm:u0|altsyncram:altsyncram_component|altsyncram_s8h1:auto_generated|ram_block1a0~porta_address_reg1'
        Info: Total cell delay = 1.141 ns ( 42.45 % )
        Info: Total interconnect delay = 1.547 ns ( 57.55 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Aug 07 15:50:28 2007
    Info: Elapsed time: 00:00:02