part2.map.eqn

基于FPGA的CPU设计 VHDL 编写

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--E1_q_a[0] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[0]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[0]_PORT_A_data_in = SW[0];
E1_q_a[0]_PORT_A_data_in_reg = DFFE(E1_q_a[0]_PORT_A_data_in, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_PORT_B_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[0]_PORT_B_address_reg = DFFE(E1_q_a[0]_PORT_B_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_PORT_A_write_enable = SW[17];
E1_q_a[0]_PORT_A_write_enable_reg = DFFE(E1_q_a[0]_PORT_A_write_enable, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = KEY[0];
E1_q_a[0]_PORT_A_data_out = MEMORY(E1_q_a[0]_PORT_A_data_in_reg, , E1_q_a[0]_PORT_A_address_reg, E1_q_a[0]_PORT_B_address_reg, E1_q_a[0]_PORT_A_write_enable_reg, , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[0] = E1_q_a[0]_PORT_A_data_out[0];


--E1_q_a[1] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[1]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[1]_PORT_A_data_in = SW[1];
E1_q_a[1]_PORT_A_data_in_reg = DFFE(E1_q_a[1]_PORT_A_data_in, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_PORT_B_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[1]_PORT_B_address_reg = DFFE(E1_q_a[1]_PORT_B_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_PORT_A_write_enable = SW[17];
E1_q_a[1]_PORT_A_write_enable_reg = DFFE(E1_q_a[1]_PORT_A_write_enable, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_clock_0 = KEY[0];
E1_q_a[1]_PORT_A_data_out = MEMORY(E1_q_a[1]_PORT_A_data_in_reg, , E1_q_a[1]_PORT_A_address_reg, E1_q_a[1]_PORT_B_address_reg, E1_q_a[1]_PORT_A_write_enable_reg, , , , E1_q_a[1]_clock_0, , , , , );
E1_q_a[1] = E1_q_a[1]_PORT_A_data_out[0];


--E1_q_a[2] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[2]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[2]_PORT_A_data_in = SW[2];
E1_q_a[2]_PORT_A_data_in_reg = DFFE(E1_q_a[2]_PORT_A_data_in, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[2]_PORT_A_address_reg = DFFE(E1_q_a[2]_PORT_A_address, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_PORT_B_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[2]_PORT_B_address_reg = DFFE(E1_q_a[2]_PORT_B_address, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_PORT_A_write_enable = SW[17];
E1_q_a[2]_PORT_A_write_enable_reg = DFFE(E1_q_a[2]_PORT_A_write_enable, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_clock_0 = KEY[0];
E1_q_a[2]_PORT_A_data_out = MEMORY(E1_q_a[2]_PORT_A_data_in_reg, , E1_q_a[2]_PORT_A_address_reg, E1_q_a[2]_PORT_B_address_reg, E1_q_a[2]_PORT_A_write_enable_reg, , , , E1_q_a[2]_clock_0, , , , , );
E1_q_a[2] = E1_q_a[2]_PORT_A_data_out[0];


--E1_q_a[3] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[3]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[3]_PORT_A_data_in = SW[3];
E1_q_a[3]_PORT_A_data_in_reg = DFFE(E1_q_a[3]_PORT_A_data_in, E1_q_a[3]_clock_0, , , );
E1_q_a[3]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[3]_PORT_A_address_reg = DFFE(E1_q_a[3]_PORT_A_address, E1_q_a[3]_clock_0, , , );
E1_q_a[3]_PORT_B_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[3]_PORT_B_address_reg = DFFE(E1_q_a[3]_PORT_B_address, E1_q_a[3]_clock_0, , , );
E1_q_a[3]_PORT_A_write_enable = SW[17];
E1_q_a[3]_PORT_A_write_enable_reg = DFFE(E1_q_a[3]_PORT_A_write_enable, E1_q_a[3]_clock_0, , , );
E1_q_a[3]_clock_0 = KEY[0];
E1_q_a[3]_PORT_A_data_out = MEMORY(E1_q_a[3]_PORT_A_data_in_reg, , E1_q_a[3]_PORT_A_address_reg, E1_q_a[3]_PORT_B_address_reg, E1_q_a[3]_PORT_A_write_enable_reg, , , , E1_q_a[3]_clock_0, , , , , );
E1_q_a[3] = E1_q_a[3]_PORT_A_data_out[0];


--C6L1 is SEG7_LUT:u6|oSEG[0]~28
C6L1 = E1_q_a[2] & !E1_q_a[1] & (E1_q_a[0] $ !E1_q_a[3]) # !E1_q_a[2] & E1_q_a[0] & (E1_q_a[1] $ !E1_q_a[3]);


--C6L2 is SEG7_LUT:u6|oSEG[1]~29
C6L2 = E1_q_a[1] & (E1_q_a[0] & (E1_q_a[3]) # !E1_q_a[0] & E1_q_a[2]) # !E1_q_a[1] & E1_q_a[2] & (E1_q_a[0] $ E1_q_a[3]);


--C6L3 is SEG7_LUT:u6|oSEG[2]~30
C6L3 = E1_q_a[2] & E1_q_a[3] & (E1_q_a[1] # !E1_q_a[0]) # !E1_q_a[2] & !E1_q_a[0] & E1_q_a[1] & !E1_q_a[3];


--C6L4 is SEG7_LUT:u6|oSEG[3]~31
C6L4 = E1_q_a[0] & (E1_q_a[1] $ !E1_q_a[2]) # !E1_q_a[0] & (E1_q_a[1] & !E1_q_a[2] & E1_q_a[3] # !E1_q_a[1] & E1_q_a[2] & !E1_q_a[3]);


--C6L5 is SEG7_LUT:u6|oSEG[4]~32
C6L5 = E1_q_a[1] & E1_q_a[0] & (!E1_q_a[3]) # !E1_q_a[1] & (E1_q_a[2] & (!E1_q_a[3]) # !E1_q_a[2] & E1_q_a[0]);


--C6L6 is SEG7_LUT:u6|oSEG[5]~33
C6L6 = E1_q_a[0] & (E1_q_a[3] $ (E1_q_a[1] # !E1_q_a[2])) # !E1_q_a[0] & E1_q_a[1] & !E1_q_a[2] & !E1_q_a[3];


--C6L7 is SEG7_LUT:u6|oSEG[6]~34
C6L7 = E1_q_a[0] & (E1_q_a[3] # E1_q_a[1] $ E1_q_a[2]) # !E1_q_a[0] & (E1_q_a[1] # E1_q_a[2] $ E1_q_a[3]);


--E1_q_a[4] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[4]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[4]_PORT_A_data_in = SW[4];
E1_q_a[4]_PORT_A_data_in_reg = DFFE(E1_q_a[4]_PORT_A_data_in, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[4]_PORT_A_address_reg = DFFE(E1_q_a[4]_PORT_A_address, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_PORT_B_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[4]_PORT_B_address_reg = DFFE(E1_q_a[4]_PORT_B_address, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_PORT_A_write_enable = SW[17];
E1_q_a[4]_PORT_A_write_enable_reg = DFFE(E1_q_a[4]_PORT_A_write_enable, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_clock_0 = KEY[0];
E1_q_a[4]_PORT_A_data_out = MEMORY(E1_q_a[4]_PORT_A_data_in_reg, , E1_q_a[4]_PORT_A_address_reg, E1_q_a[4]_PORT_B_address_reg, E1_q_a[4]_PORT_A_write_enable_reg, , , , E1_q_a[4]_clock_0, , , , , );
E1_q_a[4] = E1_q_a[4]_PORT_A_data_out[0];


--E1_q_a[5] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[5]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[5]_PORT_A_data_in = SW[5];
E1_q_a[5]_PORT_A_data_in_reg = DFFE(E1_q_a[5]_PORT_A_data_in, E1_q_a[5]_clock_0, , , );
E1_q_a[5]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[5]_PORT_A_address_reg = DFFE(E1_q_a[5]_PORT_A_address, E1_q_a[5]_clock_0, , , );
E1_q_a[5]_PORT_B_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[5]_PORT_B_address_reg = DFFE(E1_q_a[5]_PORT_B_address, E1_q_a[5]_clock_0, , , );
E1_q_a[5]_PORT_A_write_enable = SW[17];
E1_q_a[5]_PORT_A_write_enable_reg = DFFE(E1_q_a[5]_PORT_A_write_enable, E1_q_a[5]_clock_0, , , );
E1_q_a[5]_clock_0 = KEY[0];
E1_q_a[5]_PORT_A_data_out = MEMORY(E1_q_a[5]_PORT_A_data_in_reg, , E1_q_a[5]_PORT_A_address_reg, E1_q_a[5]_PORT_B_address_reg, E1_q_a[5]_PORT_A_write_enable_reg, , , , E1_q_a[5]_clock_0, , , , , );
E1_q_a[5] = E1_q_a[5]_PORT_A_data_out[0];


--E1_q_a[6] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[6]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[6]_PORT_A_data_in = SW[6];
E1_q_a[6]_PORT_A_data_in_reg = DFFE(E1_q_a[6]_PORT_A_data_in, E1_q_a[6]_clock_0, , , );
E1_q_a[6]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[6]_PORT_A_address_reg = DFFE(E1_q_a[6]_PORT_A_address, E1_q_a[6]_clock_0, , , );
E1_q_a[6]_PORT_B_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[6]_PORT_B_address_reg = DFFE(E1_q_a[6]_PORT_B_address, E1_q_a[6]_clock_0, , , );
E1_q_a[6]_PORT_A_write_enable = SW[17];
E1_q_a[6]_PORT_A_write_enable_reg = DFFE(E1_q_a[6]_PORT_A_write_enable, E1_q_a[6]_clock_0, , , );
E1_q_a[6]_clock_0 = KEY[0];
E1_q_a[6]_PORT_A_data_out = MEMORY(E1_q_a[6]_PORT_A_data_in_reg, , E1_q_a[6]_PORT_A_address_reg, E1_q_a[6]_PORT_B_address_reg, E1_q_a[6]_PORT_A_write_enable_reg, , , , E1_q_a[6]_clock_0, , , , , );
E1_q_a[6] = E1_q_a[6]_PORT_A_data_out[0];


--E1_q_a[7] is ramlpm:u0|altsyncram:altsyncram_component|altsyncram_c6a1:auto_generated|q_a[7]
--RAM Block Operation Mode: Single Port
--Port A Depth: 32, Port A Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[7]_PORT_A_data_in = SW[7];
E1_q_a[7]_PORT_A_data_in_reg = DFFE(E1_q_a[7]_PORT_A_data_in, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_PORT_A_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_PORT_B_address = BUS(SW[11], SW[12], SW[13], SW[14], SW[15]);
E1_q_a[7]_PORT_B_address_reg = DFFE(E1_q_a[7]_PORT_B_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_PORT_A_write_enable = SW[17];
E1_q_a[7]_PORT_A_write_enable_reg = DFFE(E1_q_a[7]_PORT_A_write_enable, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = KEY[0];
E1_q_a[7]_PORT_A_data_out = MEMORY(E1_q_a[7]_PORT_A_data_in_reg, , E1_q_a[7]_PORT_A_address_reg, E1_q_a[7]_PORT_B_address_reg, E1_q_a[7]_PORT_A_write_enable_reg, , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7] = E1_q_a[7]_PORT_A_data_out[0];


--C5L1 is SEG7_LUT:u5|oSEG[0]~28
C5L1 = E1_q_a[6] & !E1_q_a[5] & (E1_q_a[4] $ !E1_q_a[7]) # !E1_q_a[6] & E1_q_a[4] & (E1_q_a[5] $ !E1_q_a[7]);


--C5L2 is SEG7_LUT:u5|oSEG[1]~29
C5L2 = E1_q_a[5] & (E1_q_a[4] & (E1_q_a[7]) # !E1_q_a[4] & E1_q_a[6]) # !E1_q_a[5] & E1_q_a[6] & (E1_q_a[4] $ E1_q_a[7]);


--C5L3 is SEG7_LUT:u5|oSEG[2]~30
C5L3 = E1_q_a[6] & E1_q_a[7] & (E1_q_a[5] # !E1_q_a[4]) # !E1_q_a[6] & !E1_q_a[4] & E1_q_a[5] & !E1_q_a[7];


--C5L4 is SEG7_LUT:u5|oSEG[3]~31
C5L4 = E1_q_a[4] & (E1_q_a[5] $ !E1_q_a[6]) # !E1_q_a[4] & (E1_q_a[5] & !E1_q_a[6] & E1_q_a[7] # !E1_q_a[5] & E1_q_a[6] & !E1_q_a[7]);


--C5L5 is SEG7_LUT:u5|oSEG[4]~32
C5L5 = E1_q_a[5] & E1_q_a[4] & (!E1_q_a[7]) # !E1_q_a[5] & (E1_q_a[6] & (!E1_q_a[7]) # !E1_q_a[6] & E1_q_a[4]);


--C5L6 is SEG7_LUT:u5|oSEG[5]~33
C5L6 = E1_q_a[4] & (E1_q_a[7] $ (E1_q_a[5] # !E1_q_a[6])) # !E1_q_a[4] & E1_q_a[5] & !E1_q_a[6] & !E1_q_a[7];


--C5L7 is SEG7_LUT:u5|oSEG[6]~34
C5L7 = E1_q_a[4] & (E1_q_a[7] # E1_q_a[5] $ E1_q_a[6]) # !E1_q_a[4] & (E1_q_a[5] # E1_q_a[6] $ E1_q_a[7]);


--C4L1 is SEG7_LUT:u4|oSEG[0]~28
C4L1 = SW[2] & !SW[1] & (SW[0] $ !SW[3]) # !SW[2] & SW[0] & (SW[1] $ !SW[3]);


--C4L2 is SEG7_LUT:u4|oSEG[1]~29
C4L2 = SW[1] & (SW[0] & (SW[3]) # !SW[0] & SW[2]) # !SW[1] & SW[2] & (SW[0] $ SW[3]);


--C4L3 is SEG7_LUT:u4|oSEG[2]~30
C4L3 = SW[2] & SW[3] & (SW[1] # !SW[0]) # !SW[2] & !SW[0] & SW[1] & !SW[3];


--C4L4 is SEG7_LUT:u4|oSEG[3]~31
C4L4 = SW[0] & (SW[1] $ !SW[2]) # !SW[0] & (SW[1] & !SW[2] & SW[3] # !SW[1] & SW[2] & !SW[3]);


--C4L5 is SEG7_LUT:u4|oSEG[4]~32
C4L5 = SW[1] & SW[0] & (!SW[3]) # !SW[1] & (SW[2] & (!SW[3]) # !SW[2] & SW[0]);


--C4L6 is SEG7_LUT:u4|oSEG[5]~33
C4L6 = SW[0] & (SW[3] $ (SW[1] # !SW[2])) # !SW[0] & SW[1] & !SW[2] & !SW[3];


--C4L7 is SEG7_LUT:u4|oSEG[6]~34
C4L7 = SW[0] & (SW[3] # SW[1] $ SW[2]) # !SW[0] & (SW[1] # SW[2] $ SW[3]);


--C3L1 is SEG7_LUT:u3|oSEG[0]~28
C3L1 = SW[6] & !SW[5] & (SW[4] $ !SW[7]) # !SW[6] & SW[4] & (SW[5] $ !SW[7]);


--C3L2 is SEG7_LUT:u3|oSEG[1]~29
C3L2 = SW[5] & (SW[4] & (SW[7]) # !SW[4] & SW[6]) # !SW[5] & SW[6] & (SW[4] $ SW[7]);


--C3L3 is SEG7_LUT:u3|oSEG[2]~30
C3L3 = SW[6] & SW[7] & (SW[5] # !SW[4]) # !SW[6] & !SW[4] & SW[5] & !SW[7];


--C3L4 is SEG7_LUT:u3|oSEG[3]~31
C3L4 = SW[4] & (SW[5] $ !SW[6]) # !SW[4] & (SW[5] & !SW[6] & SW[7] # !SW[5] & SW[6] & !SW[7]);


--C3L5 is SEG7_LUT:u3|oSEG[4]~32
C3L5 = SW[5] & SW[4] & (!SW[7]) # !SW[5] & (SW[6] & (!SW[7]) # !SW[6] & SW[4]);


--C3L6 is SEG7_LUT:u3|oSEG[5]~33
C3L6 = SW[4] & (SW[7] $ (SW[5] # !SW[6])) # !SW[4] & SW[5] & !SW[6] & !SW[7];


--C3L7 is SEG7_LUT:u3|oSEG[6]~34
C3L7 = SW[4] & (SW[7] # SW[5] $ SW[6]) # !SW[4] & (SW[5] # SW[6] $ SW[7]);


--C1L1 is SEG7_LUT:u1|oSEG[0]~28
C1L1 = SW[13] & !SW[12] & (SW[11] $ !SW[14]) # !SW[13] & SW[11] & (SW[12] $ !SW[14]);


--C1L2 is SEG7_LUT:u1|oSEG[1]~29
C1L2 = SW[12] & (SW[11] & (SW[14]) # !SW[11] & SW[13]) # !SW[12] & SW[13] & (SW[11] $ SW[14]);


--C1L3 is SEG7_LUT:u1|oSEG[2]~30
C1L3 = SW[13] & SW[14] & (SW[12] # !SW[11]) # !SW[13] & !SW[11] & SW[12] & !SW[14];


--C1L4 is SEG7_LUT:u1|oSEG[3]~31
C1L4 = SW[11] & (SW[12] $ !SW[13]) # !SW[11] & (SW[12] & !SW[13] & SW[14] # !SW[12] & SW[13] & !SW[14]);


--C1L5 is SEG7_LUT:u1|oSEG[4]~32
C1L5 = SW[12] & SW[11] & (!SW[14]) # !SW[12] & (SW[13] & (!SW[14]) # !SW[13] & SW[11]);


--C1L6 is SEG7_LUT:u1|oSEG[5]~33
C1L6 = SW[11] & (SW[14] $ (SW[12] # !SW[13])) # !SW[11] & SW[12] & !SW[13] & !SW[14];


--C1L7 is SEG7_LUT:u1|oSEG[6]~34
C1L7 = SW[11] & (SW[14] # SW[12] $ SW[13]) # !SW[11] & (SW[12] # SW[13] $ SW[14]);


--SW[8] is SW[8]
--operation mode is input

SW[8] = INPUT();


--SW[9] is SW[9]
--operation mode is input

SW[9] = INPUT();


--SW[10] is SW[10]
--operation mode is input

SW[10] = INPUT();


--SW[16] is SW[16]
--operation mode is input

SW[16] = INPUT();


--KEY[1] is KEY[1]
--operation mode is input

KEY[1] = INPUT();


--KEY[2] is KEY[2]
--operation mode is input

KEY[2] = INPUT();


--KEY[3] is KEY[3]
--operation mode is input

KEY[3] = INPUT();


--SW[17] is SW[17]
--operation mode is input

SW[17] = INPUT();


--SW[0] is SW[0]
--operation mode is input

SW[0] = INPUT();


--SW[1] is SW[1]
--operation mode is input

SW[1] = INPUT();


--SW[2] is SW[2]
--operation mode is input

SW[2] = INPUT();


--SW[3] is SW[3]
--operation mode is input

SW[3] = INPUT();


--SW[4] is SW[4]
--operation mode is input

SW[4] = INPUT();


--SW[5] is SW[5]
--operation mode is input

SW[5] = INPUT();


--SW[6] is SW[6]
--operation mode is input

SW[6] = INPUT();


--SW[7] is SW[7]
--operation mode is input

SW[7] = INPUT();


--SW[11] is SW[11]
--operation mode is input

SW[11] = INPUT();


--SW[12] is SW[12]
--operation mode is input

SW[12] = INPUT();


--SW[13] is SW[13]
--operation mode is input