echo_de2.vhd

Very good info. for RS-232 echo VHDL code .

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ECHO_DE2 is
generic(divisor: integer := 3);
port(
     sysclk					: in 	std_logic; --system clock
--	 sel   					: in 	std_logic_vector(2 downto 0);
	 RX						: in 	std_logic;
	 TX						: out	std_logic;

	LCD_RS, LCD_E, LCD_ON		: OUT	STD_LOGIC;
	LCD_RW						: BUFFER STD_LOGIC;
	DATA_BUS				: INOUT	STD_LOGIC_VECTOR(7 DOWNTO 0);

--DSD
	TDI	: out std_logic;
	TDO : in std_logic;
	TMS : out std_logic;
	--SHIFT_IN : in std_logic;
	--TMS_SHIFT_IN : in std_logic
	TCK : out std_logic;
	
	
	tck_o : out std_logic;
	tck_clock : out std_logic;
	led_shift_flag : out std_logic
     );
end ECHO_DE2;

architecture arch of ECHO_DE2 is

component  br_gen  
port(
     sysclk:in std_logic;                       --system clock
     sel   :in std_logic_vector(2 downto 0);
     bclkx8:buffer std_logic;                  --baud rate X 8
     bclk  :out std_logic                       --baud rate
     );
end component;
component uart_receiver 
port(
sysclk :in std_logic; --system clock
rst_n :in std_logic; --system rest
bclkx8 :in std_logic; --detection baud rate
rxd :in std_logic; --rx of uart
rxd_readyH:out std_logic; --rxd_readyH; rising edge
RDR :out std_logic_vector(7 downto 0)--receive data 1
);
end component;
component uart_transmitter is
port(
sysclk : in std_logic; --system clock
rst_n : in std_logic; --system reset;
bclk : in std_logic; --baud rate clock
txd_startH : in std_logic; --rxd start; active high
DBUS : in std_logic_vector(7 downto 0);--Data Bus
txd_doneH : out std_logic; --transmmit finished
txd : out std_logic --txd
);
end component;
component Display is
port(	
	clk_50Mhz				: IN	STD_LOGIC;
	LCD_RS, LCD_E, LCD_ON		: OUT	STD_LOGIC;
	LCD_RW						: BUFFER STD_LOGIC;
	DATA_BUS				: INOUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
	strq1                   : in std_logic_vector(127 downto 0);
	strq2                   : in std_logic_vector(127 downto 0)
	);
end component;
component one_hot is port(
	rst, clk, pb_debounced:	in std_logic;
	pb_out:				out std_logic
);
end component;


type statetype is (idle, tdi0, tdi1, tdi2, tdi3, tdi4, tdi5, tdi6, tdi7,
                   tms0, tms1, tms2, tms3, tms4, tms5, tms6, tms7,
				   error0, error1, error2, error3, error4, error5, error6, error7);

signal s1,s2, rx_ready  : std_logic;
signal tx_start, tx_done: std_logic;
signal Rcv_data, ff		: std_logic_vector(7 downto 0);
signal pending			: std_logic;
signal baud_select		: std_logic_vector(2 downto 0);

signal Tx_data : std_logic_vector(7 downto 0);

signal buf1 : std_logic_vector(127 downto 0);
signal buf2 : std_logic_vector(127 downto 0);


signal cs : statetype;
signal next_state : statetype;

signal buf_tdi : std_logic_vector(63 downto 0);
signal buf_tms : std_logic_vector(63 downto 0);
signal buf_err : std_logic_vector(63 downto 0);
signal buf_tdo : std_logic_vector(7 downto 0);
signal send_flag : std_logic;
signal reset_send_flag :std_logic;
signal recv_flag : std_logic;

signal shift : std_logic;
signal n_shift : std_logic;
signal tms_shift : std_logic;
signal tck_out : std_logic;
signal n_tck_out : std_logic;
signal tck_clk :std_logic;


signal tck_cnt : std_logic_vector(31 downto 0);
signal shift_cnt : std_logic_vector(7 downto 0);
signal shift_flag : std_logic;
signal reset_shift_flag : std_logic;

signal RESET : std_logic;

begin

RESET <= '1';
i_oh4 : one_hot port map (RESET, sysclk, tck_out, n_shift);

i_br_gen	: br_gen port map ( sysclk, baud_select, s1, s2 );
i_uart_rcv	: uart_receiver port map ( sysclk,RESET,s1,RX,rx_ready,Rcv_data);
i_uart_trm  : uart_transmitter port map(sysclk, RESET, s2, tx_start, Tx_data, tx_done, TX );
i_display   : Display port map(sysclk, LCD_RS, LCD_E, LCD_ON, LCD_RW, DATA_BUS, buf1, buf2);

baud_select <= "000";

Tx_data <= buf_tdo;

buf1 <= X"00000000" & buf_err & X"00000000";
buf2 <= X"00000000" & buf_err & X"00000000";--X"0000000000000000";
TDI <= buf_tdi(63);
TMS <= buf_tms(63);

--shift <= not in_BTN(0);
--tms_shift <= not in_BTN(1);

tck_o <= tck_out;
tck_clock <= tck_clk;

TCK <= tck_out;
shift <= not n_shift;
led_shift_flag <= shift_flag;

buf_tdo(7 downto 1) <= "0000000";
buf_tdo(0) <= TDO;

-- F division for Clock TCK
process (sysclk)
begin
	if (sysclk'event and sysclk = '1') then
		if (tck_cnt < X"010F4240") then
			tck_cnt <= tck_cnt + 1;
		else
			tck_cnt <= X"00000000";
			tck_clk <= not tck_clk;
		end if;
	end if;
end process;

process (tck_clk)
begin
	if (tck_clk'event and tck_clk = '1') then
		tck_out <= '0';
		reset_shift_flag <= '0';
		if (shift_flag = '1' and shift_cnt < X"80") then
			tck_out <= not tck_out;
			shift_cnt <= shift_cnt + 1;
		elsif (shift_cnt = X"80") then
			reset_shift_flag <= '1';
			tck_out <= tck_clk;
			shift_cnt <= X"00";
		else
			shift_cnt <= X"00";
		end if;
	end if;

end process;

process (sysclk, send_flag)
begin
	if (send_flag = '1') then
		tx_start <= '1';
	else
		tx_start <= '0';
	end if;
end process;

process (sysclk, rx_ready, shift)
begin
	if (rising_edge(sysclk)) then

		if (rx_ready = '1') then
			case cs is
				when idle =>
					if (Rcv_data = X"57") then
						--recv_flag <= '1';
						next_state <= tdi0;
					elsif (Rcv_data = X"54") then
						next_state <= tms0;
					elsif (Rcv_data = X"4D") then
						next_state <= error0;
					else
						next_state <= idle;
					end if;
					
				when tdi0 =>
					buf_tdi(63 downto 56) <= Rcv_data;
					next_state <= tdi1;
				
				when tdi1 =>
					buf_tdi(55 downto 48) <= Rcv_data;
					next_state <= tdi2;
				
				when tdi2 =>
					buf_tdi(47 downto 40) <= Rcv_data;
					next_state <= tdi3;
				
				when tdi3 =>
					buf_tdi(39 downto 32) <= Rcv_data;
					next_state <= tdi4;
				
				when tdi4 =>
					buf_tdi(31 downto 24) <= Rcv_data;
					next_state <= tdi5;
				
				when tdi5 =>
					buf_tdi(23 downto 16) <= Rcv_data;
					next_state <= tdi6;
				
				when tdi6 =>
					buf_tdi(15 downto 8) <= Rcv_data;
					next_state <= tdi7;
				
				when tdi7 =>
					--recv_flag <= '0';
					buf_tdi(7 downto 0) <= Rcv_data;
					next_state <= idle;
				
				when tms0 =>
					buf_tms(63 downto 56) <= Rcv_data;
					next_state <= tms1;
				
				when tms1 =>
					buf_tms(55 downto 48) <= Rcv_data;
					next_state <= tms2;
				
				when tms2 =>
					buf_tms(47 downto 40) <= Rcv_data;
					next_state <= tms3;
				
				when tms3 =>
					buf_tms(39 downto 32) <= Rcv_data;
					next_state <= tms4;
				
				when tms4 =>
					buf_tms(31 downto 24) <= Rcv_data;
					next_state <= tms5;
				
				when tms5 =>
					buf_tms(23 downto 16) <= Rcv_data;
					next_state <= tms6;
				
				when tms6 =>
					buf_tms(15 downto 8) <= Rcv_data;
					next_state <= tms7;
				
				when tms7 =>
					--recv_flag <= '0';
					buf_tms(7 downto 0) <= Rcv_data;
					shift_flag <= '1';
					next_state <= idle;
					--error
				when error0 =>
					buf_err(63 downto 56) <= Rcv_data;
					next_state <= error1;
				
				when error1 =>
					buf_err(55 downto 48) <= Rcv_data;
					next_state <= error2;
				
				when error2 =>
					buf_err(47 downto 40) <= Rcv_data;
					next_state <= error3;
				
				when error3 =>
					buf_err(39 downto 32) <= Rcv_data;
					next_state <= error4;
				
				when error4 =>
					buf_err(31 downto 24) <= Rcv_data;
					next_state <= error5;
				
				when error5 =>
					buf_err(23 downto 16) <= Rcv_data;
					next_state <= error6;
				
				when error6 =>
					buf_err(15 downto 8) <= Rcv_data;
					next_state <= error7;
				
				when error7 =>
					--recv_flag <= '0';
					buf_err(7 downto 0) <= Rcv_data;
					next_state <= idle;
				
			end case; 
		
		
		end if;
		
		if (reset_shift_flag = '1') then
			shift_flag <= '0';
		end if;
		
		if (reset_send_flag = '1') then
			send_flag <= '0';
		end if;
			
		if (SHIFT = '1') then
			--if (recv_flag = '0') then 
				buf_tdi <= buf_tdi(62 downto 0) & '0';
				send_flag <= '1';
				buf_tms <= buf_tms(62 downto 0) & '1';
			--end if;
			
		end if;
	end if;
end process;

process (sysclk)
begin
	if (sysclk'event and sysclk = '1') then
			cs <= next_state;
			
			if (send_flag = '1') then
				reset_send_flag <= '1';
			else
				reset_send_flag <= '0';
			end if;
	end if;
end process;

 
end arch;