📄 adc.map.rpt
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; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 33 ;
; -- arithmetic mode ; 0 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 17 ;
; I/O pins ; 22 ;
; Maximum fan-out node ; clkcount[3] ;
; Maximum fan-out ; 14 ;
; Total fan-out ; 121 ;
; Average fan-out ; 2.20 ;
+---------------------------------------------+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |adc ; 33 (33) ; 17 ; 0 ; 22 ; 0 ; 16 (16) ; 10 (10) ; 7 (7) ; 0 (0) ; 0 (0) ; |adc ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------+
; State Machine - |adc|fsm1 ;
+-------+-------------------+
; Name ; sta_4 ;
+-------+-------------------+
; sta_2 ; 0 ;
; sta_4 ; 1 ;
+-------+-------------------+
+--------------------------------------------+
; State Machine - |adc|sta ;
+--------+--------+--------+--------+--------+
; Name ; sta.s3 ; sta.s2 ; sta.s1 ; sta.s0 ;
+--------+--------+--------+--------+--------+
; sta.s0 ; 0 ; 0 ; 0 ; 0 ;
; sta.s1 ; 0 ; 0 ; 1 ; 1 ;
; sta.s2 ; 0 ; 1 ; 0 ; 1 ;
; sta.s3 ; 1 ; 0 ; 0 ; 1 ;
+--------+--------+--------+--------+--------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 17 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 8 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 13:1 ; 5 bits ; 40 LEs ; 40 LEs ; 0 LEs ; No ; |adc|s~105 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/竞赛/adc1/adc.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Wed Apr 30 11:30:56 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adc -c adc
Info: Found 2 design units, including 1 entities, in source file adc.vhd
Info: Found design unit 1: adc-adc8is_arch
Info: Found entity 1: adc
Info: Elaborating entity "adc" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at adc.vhd(29): signal "clkcount" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc.vhd(58): signal "data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at adc.vhd(59): signal "data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at adc.vhd(60): OTHERS choice is never selected
Info: Duplicate registers merged to single register
Info: Duplicate register "count" merged to single register "clkcount[0]"
Info: State machine "|adc|fsm1" contains 2 states
Info: State machine "|adc|sta" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|adc|fsm1"
Info: Encoding result for state machine "|adc|fsm1"
Info: Completed encoding using 1 state bits
Info: Encoded state bit "sta_4"
Info: State "|adc|sta_2" uses code string "0"
Info: State "|adc|sta_4" uses code string "1"
Info: Selected Auto state machine encoding method for state machine "|adc|sta"
Info: Encoding result for state machine "|adc|sta"
Info: Completed encoding using 4 state bits
Info: Encoded state bit "sta.s3"
Info: Encoded state bit "sta.s2"
Info: Encoded state bit "sta.s1"
Info: Encoded state bit "sta.s0"
Info: State "|adc|sta.s0" uses code string "0000"
Info: State "|adc|sta.s1" uses code string "0011"
Info: State "|adc|sta.s2" uses code string "0101"
Info: State "|adc|sta.s3" uses code string "1001"
Info: Duplicate registers merged to single register
Info: Duplicate register "sta.s3" merged to single register "rd~reg0", power-up level changed
Info: Power-up level of register "sta_4" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "sta_4" with stuck data_in port to stuck value VCC
Info: Duplicate registers merged to single register
Info: Duplicate register "sta.s1" merged to single register "wr~reg0", power-up level changed
Warning: Removed always-enabled tri-state buffer s~106 feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer s~93 feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer s~80 feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer s~70 feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer s~55 feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer s~42 feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer s~28 feeding logic, open-drain buffer, or output pin
Warning: Design contains 1 input pin(s) that do not drive logic
Warning: No output dependent on input pin "int"
Info: Implemented 55 device resources after synthesis - the final resource count might be different
Info: Implemented 10 input pins
Info: Implemented 12 output pins
Info: Implemented 33 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings
Info: Processing ended: Wed Apr 30 11:30:58 2008
Info: Elapsed time: 00:00:02
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