adc.vhd

基于北京革新公司出品的EDA实验工具箱的数模转换程序。该程序将输入的5V信号从01至FF量化并通过2位数码管进行显示。量化精度为0.1v。编译环境为quartusll.5.1版本。fpga芯片为EP1

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY adc IS
PORT( clk,int :in Std_logic;
	dati :in Std_logic_vector(7 downto 0);
	wr,rd,cs :out Std_logic;
	scan :out Std_logic_vector(1 downto 0);
	s :out std_logic_vector(0 to 6)
);
END ;

ARCHITECTURE adc8is_arch OF adc IS
SIGNAL qclk,count,qint: std_logic;
signal clkcount:std_logic_vector(3 downto 0);
signal hexd:std_logic_vector(3 downto 0);
signal data: std_logic_vector(7 downto 0);
type state is (s0,s1,s2,s3);
signal sta:state;
BEGIN

qint<=int;
process(clk)
begin
	if clk'event and clk='1' then
		clkcount<=clkcount+1;
	end if;
	qclk<=clkcount(3);
end process;	

process(qclk,qint)
begin
	if qclk'event and qclk='1' then
	case sta is
		when s0 => cs<='0';wr<='0';rd<='1';sta<=s1;
		when s1 => cs<='1';wr<='1';rd<='1';
				if qint'event and qint='0' then
				sta<=s2;
				else sta<=s1;
				end if;
		when s2 => cs<='0';wr<='1';rd<='0';sta<=s3;
		when s3 => cs<='1';wr<='1';rd<='1';sta<=s0;data<=dati;
	end case;
	end if;
end process;

process(clk)
begin
	if clk'event and clk='1' then
	count<=not count;
	end if;
end process;

process(count)
begin
case count is 
	when '0' => scan <= "01";hexd<=data(7 downto 4);
	when '1' => scan <= "10";hexd<=data(3 downto 0);
	when others => scan <= "00";hexd<="0000";
end case;
end process;

s(0 to 6)<= "1111110" when hexd="0000" else
			"0110000" when hexd="0001" else
			"1101101" when hexd="0010" else
			"1111001" when hexd="0011" else
			"0110011" when hexd="0100" else
			"1011011" when hexd="0101" else
			"1011111" when hexd="0110" else	
			"1110000" when hexd="0111" else
			"1111111" when hexd="1000" else
			"1111011" when hexd="1001" else
			"1110111" when hexd="1010" else
			"0011111" when hexd="1011" else
			"1001110" when hexd="1100" else
			"0111101" when hexd="1101" else
			"1001111" when hexd="1110" else
			"1000111" when hexd="1111" else
			"ZZZZZZZ";
END adc8is_arch;